Motorola DragonBall MC9328MX1, Reference Manual

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Functional Overview
MOTOROLA SDRAM Memory Controller 24-3
24.3 Functional Overview
The SDRAM Controller consists of 7 major blocks, including the SDRAM command controller, page and
bank address comparators, row and column address multiplexer, data aligner–multiplexer, configuration
registers, refresh request counter, and the powerdown timer.
24.3.1 SDRAM Command Controller
The command controller handles the majority of the actions within the SDRAM controller including
sequencing accesses to the memories, initializing the DRAM, keeping track of active banks within each
memory region, scheduling refresh operations, transitioning into and out of low-power modes, and
controlling the address and data multiplexers.
24.3.2 Page and Bank Address Comparators
There are a total of 8 address comparators. Each chip-select has a unique comparator for each of its four
banks. The comparators are used to determine if a requested access falls within the address range of a
currently active DRAM page.
24.3.3 Row and Column Address Multiplexer
All synchronous DRAMs incorporate a multiplexed address bus, although the address folding points vary
according to memory density, data I/O size, and processor data bus width. The address folding point is
described as the point where the column address bits end and the row (or bank) address begin. The
SDRAM Controller takes these variables into account and provides the proper alignment of the
multiplexed address through the row and column address multiplexer, non-multiplexed address pins, and
the connections between the controller and the memory devices.
24.3.4 Data Aligner and Multiplexer
The data alignment block is responsible for aligning the data between the internal AHB bus and the
external memory device(s) including little endian byte swapping.
24.3.5 Configuration Registers
Configuration registers determine the operating mode of the SDRAM Controller by selecting memory
device density and bus width, the number of memory devices, CAS latency, row-to-column delay, and the
burst length. Enable bits are provided for refresh and the auto-powerdown timer. Control bits provide a
mechanism for software-initiated SDRAM initialization, SDRAM mode register settings, and all bank
precharge and auto-refresh cycles.
24.3.6 Refresh Request Counter
SDRAM memories require a periodic refresh to retain data. The refresh request counter generates requests
to the SDRAM Command Controller to perform these refresh cycles. Requests are scheduled according to
a 32 kHz clock input with 1, 2, or 4 refresh cycles generated per clock.