Motorola DragonBall MC9328MX1, Reference Manual

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19-30 MC9328MX1 Reference Manual MOTOROLA
LCD Controller
19.4.11 Sharp Configuration 1 Register
For 2 bpp modes, full black and full white are the two predefined display levels. The other two
intermediate gray-scale shading densities can be adjusted within the Sharp Configuration 1 Register. This
register also controls the relative delay timing of the CLS, REV and PS. The TFT timing diagram that
shows the relationship between these signals is shown in Figure 19-18.
LSCR1 Sharp Configuration 1 Register
Addr
0x00205028
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PS_RISE_DELAY CLS_RISE_DELAY
TYPE rw rw rw rw rw rw r r rw rw rw rw rw rw rw rw
RESET
0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
0x0400
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REV_TOGGLE_DELAY GRAY 2 GRAY 1
TYPE r r r r rw rw rw rw rw rw rw rw rw rw rw rw
RESET
0 0 0 0 0 0 1 1 0 1 1 1 0 0 1 1
0x0373
Table 19-19. Sharp Configuration 1 Register Description
Name Description Settings
PS_RISE_DELAY
Bits 31–26
PS Rise Delay —Controls the delay of
the rising edge of PS relative to the
falling edge of CLS. Delay is
measured in LCDC_CLK (PerCLK2)
periods.
000000 = 0 LSCLK periods
000001 = 1 LSCLK period
...
111111 = 63 LSCLK
periods
Reserved
Bits 25–24 Reserved—These bits are reserved and should read 0.
CLS_RISE_DELAY
Bits 23–16
CLS Rise Delay —Controls the delay
of the rising edge of CLS relative to
the last LD of the line. Delay is
measured in LCDC_CLK (PerCLK2)
periods.
00000000 = 1 LSCLK
period
00000001 = 2 LSCLK
periods
...
11111111 = 256 LSCCLK
periods
Reserved
Bits 15–12 Reserved—These bits are reserved and should read 0.
REV_TOGGLE_DELAY
Bits 11–8
REV Toggle Delay —Controls the
transition delay of REV relative to the
last LD of the line. Delay is measured
in LCDC_CLK (PerCLK2) periods.
0000 = 1 LSCLK period
0001 = 2 LSCLK periods
...
1111 = 16 LSCLK periods