Motorola DragonBall MC9328MX1, Reference Manual

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12-6 MC9328MX1 Reference Manual MOTOROLA
Phase-Locked Loop and Clock Controller
CSCR Clock Source Control Register
Addr
0x0021B000
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLKO_SEL USB_DIV SD_CNT
SPLL_
RESTART
MPLL_
RESTART
CLK16
_SEL
OSC
_EN
System
_SEL
TYPE rw rw rw rw rw rw rw rw r rw rw r r rw rw rw
RESET
0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0
0x0F00
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESC BCLK_DIV SPEN MPEN
TYPE rw r rw rw rw rw r r r r r r r r rw rw
RESET
1 0 1 0 1 1 0 0 0 0 0 0 0 0 1 1
0xAC03
Table 12-5. Clock Source Control Register Description
Name Description Settings
CLKO_SEL
Bits 31 – 29
CLKO Select —Selects the clock signal source
that is output on the CLKO pin.
000 = PERCLK1
001 = HCLK
010 = CLK48M
011 = CLK16M
100 = PREMCLK
101 = FCLK
USB_DIV
Bits 28 – 26
USB Divider —Contains the integer divider value
used to generate the CLK48M signal for the USB
modules.
000 = System PLL clock divide by 1
001 = System PLL clock divide by 2
.
.
.
111 = System PLL clock divide by 8
SD_CNT
Bits 25 – 24
Shut-Down Control —Contains the value that sets
the duration of System PLL clock output after 0 is
written to the SPEN bit. The power controller
requests the bus before System PLL shutdown.
Any unmasked interrupt event enables the System
PLL.
00 = System PLL shuts down after next
rising edge of CLK32 is detected and
the current bus cycle is completed. A
minimum of 16 HCLK cycles is
guaranteed from writing “0” to SPEN
bit.
01 = System PLL shuts down after the
second rising edge of CLK32 is
detected and the current bus cycle is
completed.
10 = System PLL shuts down after the third
rising edge of CLK32 is detected and
the current bus cycle is completed.
11 = System PLL shuts down after forth
rising edge of CLK32 is detected and
the current bus cycle is completed.
Reserved
Bit 23 Reserved—This bit is reserved and should read 0.