Motorola DragonBall MC9328MX1, Reference Manual

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21-18 MC9328MX1 Reference Manual MOTOROLA
Memory Stick Host Controller (MSHC) Module
Reserved
Bits 12–8 Reserved—These bits are reserved and should read 0.
RDY
Bit 7
Ready —Indicates whether communications with the memory stick are in
progress or have ended. Clear by writing to the Memory Stick Command
Register. MSIRQ asserts when RDY transitions from
0
to
1
to signal that
the protocol has ended. An internal interrupt request (MSIRQ) for this bit
is negated by reading the MSICS register (when INTEN = 1).
Note: Data cannot be written to the Memory Stick Command Register
while the protocol is executing.
0 = Protocol in progress
1 = Protocol ended
SIF
Bit 6
Serial I/F Interrupt —Indicates that a Serial I/F Interrupt has been
generated. For SIF, an interrupt signal is output separately from RDY.
(See Figure 21-3, “Memory Stick Interrupt Transfer State (BS0)
Operation,” on page 21-6).
Cleared by writing to the Memory Stick Command Register.
An internal interrupt request (MSIRQ) for this bit is negated by reading
the MSICS register (when INTEN = 1).
0 = No serial I/F Interrupt
1 = Serial I/F Interrupt
generated
DRQ
Bit 5
Data Transfer Request —Indicates that a data transfer request condition
occurred. The DRQ bit can be changed only when the MSICS bit DRQSL
is 1. Cleared by writing to the FIFO (when PID is a write command) or
reading the FIFO (when PID is a read command), and then an internal
interrupt request (MSIRQ) is negated (when DRQSL = 1). Also the
interrupt request (MSIRQ) for this bit is negated by reading the MSICS
register.
NOTE:
When the DRQEN bit of the MSDRQC register is set to
0
, the internal
DMA request signal is not generated even when this DRQ bit is 1.
0 = No data transfer
request condition
occurs
1 = Data transfer request
condition occurs
PIN
Bit 4
Parallel Input —Indicates whether the parallel input level has changed
on pins MS_PI [1:0]. This bit is cleared by reading the MSPPCD. An
internal interrupt request (MSIRQ) for this bit is negated by reading the
MSICS register (when INTEN = 1).
0 = Parallel Input level
unchanged
1 = Parallel Input level
change
Reserved
Bit 3 Reserved—This bit is reserved and should read 0.
FAE
Bit 2
FIFO Access Error —Indicates that a FIFO access error occurred.
Cleared when the MSFAECS register is read. This status bit is
enabled/disabled with the FAEEN bit of the MSFAECS register. An
internal interrupt request (MSIRQ) for this bit is negated by reading the
MSICS register (when INTEN = 1).
0 = No FIFO access error
1 = FIFO access error
occurred
CRC
Bit 1
CRC Error —Indicates that a CRC error occurred. Cleared when data is
written to the Memory Stick Command Register.
BS output is set to Low level when a CRC error occurs. Also, RDY
becomes 1 and an interrupt signal is output. An internal interrupt request
(MSIRQ) for this bit is negated by reading the MSICS register (when
INTEN = 1).
0 = No CRC error
1 = CRC error occurred
Table 21-11. Memory Stick Interrupt Control/Status Register Description (Continued)
Name Description Setting