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Services Power Management Unit
Copyright © 12/13/06 Marvell
CONFIDENTIAL
Doc. No. MV-TBD-00 Rev. A
December 13, 2006
Document Classification: Proprietary Information
Page 187
Not approved by Document Control. For review only.
c. The MPMU asserts SYS_EN, enabling the external high-voltage power supplies. The external voltage
regulators supply VCC_MVT first, followed by VCC_CARD1, VCC_CARD2, VCC_PLL, VCC_BG,
VCC_OSC13M, VCC_MEM, VCC_DF, VCC_MSL, VCC_CI, VCC_LCD, VCC_IO1, VCC_IO3,
VCC_BIAS(PXA310 processor), VCC_ULPI (PXA310 processor) and VCC_USB(PXA300
Processor).
d. The MPMU asserts PWR_EN and the power manager I
2
C module sends I
2
C commands, enabling the
external low-voltage power supplies: VCC_APPS and VCC_SRAM.
2. The internal power domains are powered up.
3. The MPMU negates the nRESET_OUT pin.
Note:
The power supply ramp times and sequences, as well as the delay between the power supply
transitions and nRESET_OUT de-assertion, are described in the PXA300 Processor and PXA310
Processor Electrical, Mechanical, and Thermal Specification. Permanent damage to the device
may result if any other supply power-up sequence is followed.
Normal boot-up sequencing begins with all units beginning in their predefined reset conditions. The core
software must examine the “Application Subsystem Reset Status register” (ARSR) to determine the reset source.
8.6.2
Hardware Reset
Hardware reset is invoked when the nRESET pin is asserted and all units are reset to a known state. Hardware
reset is intended for complete and total reset purposes only.
8.6.2.1
Behavior During Hardware Reset
During hardware reset, all internal registers and processes are held at their defined reset states. While the
nRESET pin is asserted, the only activity inside the subsystems is the stabilization of the timekeeping oscillator.
The remaining internal clocks are stopped and the chip is fully static. Additionally, all pins assume their reset
states, including SYS_EN which is negated. The nRESET_OUT pin is asserted when the nRESET pin is
asserted.
8.6.2.2
Invoking Hardware Reset
Hardware reset is invoked when an external source pulls the nRESET pin low. There is no way
of masking or
disabling the propagation of the nRESET pin value into the MPMU. Upon the assertion of the nRESET pin, reset
state is entered regardless of the previous mode. The nRESET_OUT pin is asserted when the nRESET pin is
asserted. To enter hardware reset, nRESET must be held low long enough to allow internal stabilization and
propagation of the reset state. Refer to the PXA300 Processor and PXA310 Processor Electrical, Mechanical,
and Thermal Specification for nRESET timing specifications.
The sequence for hardware reset is:
1. The nRESET pin is asserted for a period of time described in the PXA300 Processor and PXA310 Processor
Electrical, Mechanical, and Thermal Specification. The MPMU asserts nRESET_OUT and negates
SYS_EN.
2. The nRESET pin is de-asserted. VCC_BBATT must be stable prior to the de-assertion of nRESET or
operation is not guaranteed, and permanent damage to the chip may result.
3. The timekeeping oscillator waits for stabilization, if not stabilized already.