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PXA300 Processor and PXA310 Processor
Vol. I: System and Timer Configuration Developers Manual
Doc. No. MV-TBD-00 Rev. A
CONFIDENTIAL
Copyright © 12/13/06 Marvell
Page 144
Document Classification: Proprietary Information
December 13, 2006
Not approved by Document Control. For review only.
6.3.4
Timekeeping Clock Output (CLK_TOUT)
The CLK_TOUT signal outputs a buffered version of the TXTAL_IN oscillator input. The CLK_TOUT signal
can be used to provide a 32.768-kHz clock for output to the external system. The CLK_TOUT signal can be
enabled and disabled in S0, S2, or S3 states using the respective OSCC[TENSx] bit.
6.3.5
VCTCXO Enable (VCTCXO_EN)
VCTCXO_EN signal is asserted to enable an external clock source for the processor oscillator clock.
VCTCXO_EN is asserted when the services unit CCU is ready to receive the processor oscillator input clock.
6.4
Operation
6.4.1
System Clock Requirements
The processor oscillator crystal frequency is 13 MHz. If an external clock source is used, the clock source
frequency must be13 MHz .
6.4.2
Functional Description
This section provides a functional description of the services unit CCU operation, including clock generation and
frequency selection and enabling.
Primary clocks are as follows:
•
Timekeeping oscillator clock: 32.768 kHz
•
Processor oscillator clock: 13 MHz
•
Core PLL provides two clocks:
— Turbo clock is 13 MHz * XL * XN, . The turbo clock is used by the core only.
— Run clock is 13 MHz * XL, and is used by the core and the switch module within the application
subsystem.
Refer to
Table 4-4, “Core PLL, Turbo and Run Output Frequencies” on page 4-11
for the possible
combinations.
•
System PLL clock is 624 MHz. Most of the fixed-frequency clocks are derived from this clock.
•
The secondary peripheralPLL clock is 13 MHz * GL * 2, where GL can be 10. The secondary peripheral
PLL clock operates at a fixed frequency of 520 MHz divided by 2 to 260 MHz for the DDR SDRAM clock.
•
Ring oscillator clock is 120 MHz ± 15% (D0 mode) or 40 MHz ± 5% (D1 mode)