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VELL CONFIDENTIAL,
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69rlq62d-f714peg4 * Memec (Headquar
ter
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Tec
h,
Insight,
Impact
MAR
VELL CONFIDENTIAL,
UNDER ND
A# 12101050
69r
lq62d-f714peg4 * Memec (Headquar
ters) - Unique
T
ech, Insight, Impact * UNDER ND
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UTHORIZED DISTRIB
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OHIBITED
PXA300 Processor and PXA310 Processor
Vol. I: System and Timer Configuration Developers Manual
Doc. No. MV-TBD-00 Rev. A
CONFIDENTIAL
Copyright © 12/13/06 Marvell
Page 232
Document Classification: Proprietary Information
December 13, 2006
Not approved by Document Control. For review only.
8.9.8
Power Manager Mask Event Register (PMER)
PMER, defined in
, is used to provide software control of the power manager event detection and
execution. PMER provides control of the following events:
•
GPIO reset — Masks the execution of the GPIO reset sequence in the BPMU.
— When the GPIO reset event is not masked (PMER[GPME] is clear) and the nGPIO_RESET signal is
asserted, the BPMU places the external memory into self-refresh and then GPIO reset is propagates to
the application subsystem. All units in the application subsystem are reset to their predefined states.
— When the GPIO reset event is masked (PMER[GPME] is set) and the nGPIO_RESET signal is asserted,
the MPMU will not propagate GPIO reset to the BPMU. The external memory controller will not be put
into self-refresh mode and the application subsystem will not be reset.
•
Battery Fault — Masks the detection of nBATT_FAULT assertion.
— When the battery fault event is not masked (PMER[BFME] is clear) and the nBATT_FAULT signal is
asserted the MPMU will send an interrupt to the application core if PCMR[BIE] = 1 or will enter S3
mode if PCMR[BIE] = 0.
— When the battery fault event is masked (PMER[BFME] is set to 1), if PCMR[BIE] = 0 and the
nBATT_FAULT signal is asserted, the MPMU will enter S3 mode as expected. PMER[BFME] has no
effect on S3 entery when PCMR[BIE] = 0.
— When the battery fault event is masked (PMER[BFME] is set to 1), if PCMR[BIE] = 1 and the
nBATT_FAULT signal is asserted , the MPMU will take no action due to the nBATT_FAULT assertion.
The MPMU will not send an interrupt to the core when PCMR[BIE] = 1.
•
Application core PLL throttle — Masks the execution of the application core PLL frequency reduction due
to a high temperature condition.
— When the throttle event is not masked (PMER[TME] is clear) and the high-temperature condition that
would trigger an application core PLL frequency reduction occurs, the MPMU will send a frequency
change request to the BCCU.
— When the throttle event is masked (PMER[TME] is set) and the high-temperature condition that would
trigger an application core PLL frequency reduction occurs, the MPMU detects the condition, but does
not send a frequency change request to the BCCU. If the BPMU or MPMU enters a low power state
before PMER[TME] is cleared, the high-temperature frequency change request is cleared and will not
be executed until another high-temperature condition is detected.
•
Wakeup Enable— Enables the detection of EXT_WAKEUP<1:0> and RTC wakeup prior to completing the
low power mode entry sequence.
— When the external wakeup event is enabled, the MPMU will detect wakeup events for S2 and S3 entry
even though the low power mode entry sequence has not completed. If EWEE is set, the MPMU will
detect a transition on EXT_WAKEUP<1:0> and then when S2 and S3 entry sequence is entered, will
exit the low power mode if the detected wakeup event is enabled.
— When EWEE is clear, the MPMU will not detect transitions on EXT_WAKEUP<1:0> until a low power
mode entry sequence has completed. For S2 entry, the MPMU will not detect wakeup events until
PWR_EN is asserted. For S3 entry, the MPMU will not detect wakeup events until SYS_EN is asserted.