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PXA300 Processor and PXA310 Processor
Vol. I: System and Timer Configuration Developers Manual
Doc. No. MV-TBD-00 Rev. A
CONFIDENTIAL
Copyright © 12/13/06 Marvell
Page 46
Document Classification: Proprietary Information
December 13, 2006
Not approved by Document Control. For review only.
2.6
Peripheral Access on Internal System Buses
Peripherals on System Bus 1 (for example, LCD controller) and System Bus 2 (for example, 2D graphics
controller) mostly use their own internal DMA to access the system. The exception to this is the data flash
interface, which uses the system DMA to transfer data. The core can read/write the internal registers within these
peripherals, but typically, FIFOs within these peripherals cannot be read or written to by the core - the internal
DMA within the peripheral handles all reads and writes to these FIFOs. Refer to the individual peripheral
chapters for more information.
2.7
DMA/Peripheral Split Transactions
Processor accesses to the peripheral bus are, by default, split (posted) operations.
For a read operation, there are two system-bus transactions: an initial transaction to send the request, and a
separate data transfer to return the read data. During the gap between these two operations, the system bus is
relinquished and can be used by other devices.
For a write operation, the system-bus transaction completes when the write has transferred over to the
DMA/bridge rather than waiting until it reaches the actual peripheral.
In both cases, operations complete on the peripheral bus in strict order of issue on the system bus. However, for
writes in particular, completion of the write (as seen by the processor) does not mean that the write has taken
effect. To guarantee that a write has taken effect, a read to any peripheral bus location is required (once the read
has completed all earlier writes have taken effect).
2.8
System Bus Arbiters
The two internal high-speed system buses support multiple clients — the bridge (with DMA controller), the LCD
controller, the USB host controllers, camera interface, data flash controller and SGPR on System Bus 1 and 2-D
graphics and USB2.0 client on System Bus 2. Each system bus is implemented as a multiplexer (versus a
three-state approach) and the clients are allowed to request the bus without any limitations. The arbitration for
bus access is performed by an arbiter on each bus, which is programmable through its ARB_CNTRL register.
The arbiters have the following features:
•
Programmable client weights
•
Software selectable bus parking
•
Bus locking
2.9
System Access Latencies
There are multiple masters (for example, DMA, USB host, and LCD controller) in the system. All accesses to the
external memory from any of these masters flow through the switch and memory controllers. The memory
controllers have limited internal buffers that function as a FIFO. All requests are executed in the order received.