69rlq62d-f714peg4 * Memec (Headquar
ter
s) - Unique
Tec
h,
Insight,
Impact
MAR
VELL CONFIDENTIAL,
UNDER ND
A# 12101050
69rlq62d-f714peg4 * Memec (Headquar
ter
s) - Unique
Tec
h,
Insight,
Impact
MAR
VELL CONFIDENTIAL,
UNDER ND
A# 12101050
69r
lq62d-f714peg4 * Memec (Headquar
ters) - Unique
T
ech, Insight, Impact * UNDER ND
A# 12101050
MAR
VELL CONFIDENTIAL - UNA
UTHORIZED DISTRIB
UTION OR USE STRICTL
Y PR
OHIBITED
PXA300 Processor and PXA310 Processor
Vol. I: System and Timer Configuration Developers Manual
Doc. No. MV-TBD-00 Rev. A
CONFIDENTIAL
Copyright © 12/13/06 Marvell
Page 218
Document Classification: Proprietary Information
December 13, 2006
Not approved by Document Control. For review only.
c. Write to the Voltage Change Control register (VCC1) to select the ADTV2 and SDTV2 registers for the
voltage settings and enable the voltage change.
Note:
The ADTV2, SDTV2, and VCC1 are registers defined in the power-management integrated
circuit (PMIC) used to interface to the processor.
2. Once the new voltages have been achieved, the processor CCU switches the changed frequency to the
programmed values.
3. The frequency change sequence exits at the new voltage and frequency.
The following sequence occurs if the maximum core turbo frequency is being decreased:
1. If selected, the processor CCU switches the core clocks to the system PLL, otherwise the core clocks are
disabled. If selected, the system PLL frequency selected by the XSPCLK bits in the Application Subsystem
Clock Configuration register (ACCR) must be less than or equal to the current core frequency.
2. The core PLL is programmed to use the new XL and XN values.
3. The PWR_I
2
C initiates a voltage-change sequence to decrease VCC_APPS and VCC_SRAM
to the voltages
required by the new XL, XN, and MTS settings. Note that the VCC_SRAM supply is not set to a voltage
lower than the highest voltage required by the application subsystem. The voltage-change sequence consists
of the following which are automatically sent by the PWR_I2C unit:
a. Write to the external regulator VCC_APPS DVM Target Voltage 2 register (ADTV2) to set the
VCC_APPS output voltage.
b. Write to the external regulator VCC_SRAM DVM Target Voltage 2 register (SDTV2) to set the
VCC_SRAM output voltage.
c. Write to the Voltage Change Control register (VCC1) to select the ADTV2 and SDTV2 registers for the
voltage settings and enable the voltage change.
Note:
The ADTV2, SDTV2, and VCC1 are registers defined in the power-management integrated
circuit (PMIC) used to interface to the processor.
4. The processor CCU switches the core clocks to the core PLL clock outputs.
5. The frequency-change sequence exits at the frequency. The voltage change may not be completed when the
frequency-change sequence completes .
8.8.3.3
Coupling Voltage Change with Power Modes
The following sequence occurs if VCC_APPS and VCC_SRAM must be changed due to the low power mode
entry.
1. The PMU initiates a voltage-change sequence to change VCC_APPS and VCC_SRAM supplies to the
voltage required by the new low power mode being entered. This voltage-change sequence consists of the
following which are automatically sent by the PWR_I2C unit:
a. Write to the external regulator VCC_APPS DVM Target Voltage 2 register (ADTV2) to set the
VCC_APPS output voltage.
b. Write to the external regulator VCC_SRAM DVM Target Voltage 2 register (SDTV2) to set the
VCC_SRAM output voltage.
c. Write to the Voltage Change Control register (VCC1) to select the ADTV2 and SDTV2 registers for the
voltage settings and enable the voltage change.