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Introduction
Copyright © 12/13/06 Marvell
CONFIDENTIAL
Doc. No. MV-TBD-00 Rev. A
December 13, 2006
Document Classification: Proprietary Information
Page 19
Not approved by Document Control. For review only.
Introduction
1
The PXA300 processor or PXA310 processors are high-performance, low-power microprocessors providing a
rich feature set optimized for personal digital assistant applications. The PXA300 processor or PXA310
processor complies with the ARM* Instruction Set Architecture V5TE. It utilizes the Intel XScale
®1
technology
building blocks featuring:
•
A super-pipelined RISC microarchitecture, providing performance for demanding applications.
•
Wireless Intel SpeedStep
®
Power Manager technology, enabling dynamic scaling of computing performance
and power consumption based on application requirements.
This chapter presents an overview of the PXA300 processor or PXA310 processor. It also describes
documentation conventions and related documents referenced throughout the four-volume set.
1.1
About This Manual
The PXA300 Processor and PXA310 Processor Developers Manual consists of four volumes.
•
This volume
,
Vol. I: PXA300 Processor and PXA310 Processor Developers Manual: System and Timer
Configuration, presents an overview of the PXA300 processor or PXA310 processor. It describes product
features and device-specific configuration information, such as the memory map and signal multiplexing,
and provides an overview of clocking and power management features. This volume also provides
detailed
information on system-wide functions, such as the memory switch, clock control, power management,
1-Wire bus, DMA controller, general-purpose I/O (GPIO) controller, real-time clock, operating system
timers, system bus arbitration, and interrupt control.
•
Vol. II: PXA300 Processor and PXA310 Processor Developers Manual: Memory Controller Configuration
provides
detailed information on the memory interfaces and configuration of the memory controllers. The
dynamic memory controller, static memory controller, external memory pin interface (EMPI), data flash
controller, data flash interface (DFI), internal memory, and MultiMediaCard/SD/SDIO controller are all
described in this volume.
•
Vol. III: PXA300 Processor and PXA310 Processor Developers Manual: Graphics and Input Controller
Configuration
provides
detailed information on the configuration of the LCD controller and mini-LCD
controller, Intel
®
Quick Capture Camera Interface, and keypad controller.
•
Vol. IV: PXA300 Processor and PXA310 Processor Developers Manual: Serial Controller Configuration
provides
detailed information on the configuration of the serial controllers, including USB 1.0 client and
host controllers, USB 2.0, synchronous serial protocol (SSP) ports, AC ‘97 controller, UARTs, consumer
infrared port, pulse width modulator controllers, universal subscriber ID interfaces, and the I
2
C bus interface
unit.
The PXA300 Processor and PXA310 Processor Developers Manual is intended for experienced programmers of
ARM* Architecture V5TE-compliant processors. This manual assumes that the programmer has a working
knowledge of the vocabulary and principles of embedded-systems programming. The Intel XScale
®
core and the
Wireless MMX
™
2 media enhancement technology are not described in this manual. For more information, refer
1.
Intel XScale® is a trademark or registered trademark of Intel Corporation and its subsidiaries in the United States and other countries.
Vol. I of this partially rebranded Developer Manual has not been edited
by Tech Pubs.