69rlq62d-f714peg4 * Memec (Headquar
ter
s) - Unique
Tec
h,
Insight,
Impact
MAR
VELL CONFIDENTIAL,
UNDER ND
A# 12101050
69rlq62d-f714peg4 * Memec (Headquar
ter
s) - Unique
Tec
h,
Insight,
Impact
MAR
VELL CONFIDENTIAL,
UNDER ND
A# 12101050
69r
lq62d-f714peg4 * Memec (Headquar
ters) - Unique
T
ech, Insight, Impact * UNDER ND
A# 12101050
MAR
VELL CONFIDENTIAL - UNA
UTHORIZED DISTRIB
UTION OR USE STRICTL
Y PR
OHIBITED
PXA300 Processor and PXA310 Processor
Vol. I: System and Timer Configuration Developers Manual
Doc. No. MV-TBD-00 Rev. A
CONFIDENTIAL
Copyright © 12/13/06 Marvell
Page 372
Document Classification: Proprietary Information
December 13, 2006 10:46 am,
Preliminary
Not approved by Document Control. For review only.
21
R/W
UART2
UART2
0 = Masked.
1 = UART2 interrupt is not to be masked.
20
R/W
UART3
UART3
0 = Masked.
1 = UART3 interrupt is not to be masked.
19
—
—
reserved
18
R/W
I2C
I
2
C
0 = Masked.
1 = I
2
C interrupt is not to be masked.
17
R/W
LCD
LCD Controller
0 = Masked.
1 = LCD controller interrupt is not to be masked.
16
R/W
SSP2
SSP 2
0 = Masked.
1 = SSP 2 service request interrupt is not to be masked.
15
R/W
USIM1
USIM 1
0 = Masked.
1 = Smart card interface status/error interrupt is not to be masked.
14
R/W
AC97
AC97
0 = Masked.
1 = AC97 interrupt is not to be masked.
13
R/W
SSP4
SSP4
0 = Masked.
1 = I
2
S interrupt is not to be masked.
12
R/W
PML
Performance Monitor Unit
0 = Masked.
1 = PML interrupt is not to be masked.
11
R/W
USBC
USB Client
0 = Masked.
1 = USB client interrupt is not to be masked.
Table 12-9. ICMR Bit Definitions (Sheet 2 of 3)
Physical Address
0x40D0_0004
Coprocessor Register: CP6, CR1
ICMR
Interrupt Controller
User
Settings
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RTC_AL
RTC_HZ
OS
T_
3
OS
T_
2
OS
T_
1
OS
T_
0
DM
A
C
S
SP1
MM
C
1
UA
RT
1
UA
RT
2
UA
RT
3
rese
rv
e
d
I2
C
LCD
S
SP2
US
IM1
AC97
S
SP4
PM
L
US
BC
GP
IO_
x
GP
IO_
1
GP
IO_
0
O
S
T
_4_1
1
PWR
_
I2
C
rese
rv
e
d
KE
Y
P
A
D
U
S
BH1
U
S
BH2
MS
L
1
S
SP3
Reset
0
0
0
0
0
0
0
0
0
0
0
0
?
0
0
0
0
0
0
0
0
0
0
0
0
0
?
0
0
0
0
0
Bits
Access
Name
Description