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Interrupt Controller
12
Copyright © 12/13/06 Marvell
CONFIDENTIAL
Doc. No. MV-TBD-00 Rev. A
December 13, 2006 10:46 am,
Preliminary
Document Classification: Proprietary Information
Page 375
Not approved by Document Control. For review only.
12.5.5
Interrupt Controller Level Registers (ICLR and ICLR2)
The Interrupt Controller Level registers (ICLR and ICLR2) control whether a pending interrupt generates an FIQ
or an IRQ interrupt. If a pending interrupt is unmasked, the corresponding ICLR (or ICLR2) bit field is decoded
to select which CPU interrupt is asserted.
and
show the location of all interrupt-level
bits in the ICLR and the ICLR2. The ICLR and the ICLR2 registers are initialized to all zeros at reset and
software must configure them to reflect the correct value for normal operation.
9
R/W
MMC 2
MMC 2
0 = Masked.
1 = Interrupt is not to be masked.
8
—
—
reserved
7
R/W
GRAPHICS
Graphics
0 = Masked.
1 = Interrupt is not to be masked.
6
R/W
USIM 2
USIM 2
0 = Masked.
1 = Interrupt is not to be masked.
5
—
—
reserved
4
—
—
reserved
3
—
—
reserved
2
R/W
CONSUMER
IR
Consumer IR
0 = Masked.
1 = Interrupt is not to be masked.
1
R/W
CIF
Capture Interface
0 = Masked.
1 = Interrupt is not to be masked.
0
—
—
reserved
Table 12-10. ICMR2 Bit Definitions (Sheet 2 of 2)
Physical Address
0x40D0_00A0
Coprocessor Register: CP6, CR7
ICMR2
Interrupt Controller
User
Settings
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
reserved
reserved
reserved
rese
rv
e
d
BCCU
DME
M
C
W
AKE
UP
1
W
AKE
UP
0
rese
rv
e
d
S
G
P MP
MU
US
B 2
NAN
D INF
ONE
WI
RE
rese
rv
e
d
rese
rv
e
d
MM
C
2
rese
rv
e
d
GRA
P
HICS
U
S
IM
2
rese
rv
e
d
resreve
d
rese
rv
e
d
C
O
NS
UM
E
R
I
R
CI
F
rese
rv
e
d
Reset ?
?
?
?
?
?
?
?
?
?
?
0
0
0
0
?
0
0
0
0
?
?
0
?
0
0
?
?
?
0
0
?
Bits
Access
Name
Description