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Services Power Management Unit
Copyright © 12/13/06 Marvell
CONFIDENTIAL
Doc. No. MV-TBD-00 Rev. A
December 13, 2006
Document Classification: Proprietary Information
Page 217
Not approved by Document Control. For review only.
4. Initiate the application core PLL frequency change by writing the PXA300 processor clock-control unit
coprocessor 14 clock by setting the F-bit to 1.
A programmable module frequency change is initiated by writing to the ACCR in the slave clocks unit. Perform
the following to enact a programmable module frequency change with a VCC_APPS and VCC_SRAM voltage
change:
1. Set SMCFS, SFLFS, HSS or DMSFS in the “Application Subsystem Clock Configuration Register
(ACCR)” in the “Slave Clock Control Unit”
When software initiates an application core PLL or programmable module frequency change, the PWR_I
2
C
initiates a VCC_APPS
and VCC_SRAM
voltage change to increase or decrease the voltage as needed for the
requested output frequency. Additionally, for an application core PLL frequency change, the voltage of these two
supplies may be changed as needed based on the MTS bit-field value. The following sequence occurs if the
application core frequency (ACCR[XL]) is being increased:
1. If selected, the slave CCU switches the application core clocks to the system PLL. Otherwise, the
application core clocks are disabled.
2. The PMU initiates a voltage-change sequence to increase VCC_APPS and VCC_SRAM supplies to the
voltage required by the new XL and XN settings in the Application Subsystem Clock Configuration register
(ACCR) and MTS settings in the Application Subsystem Power Status/Configuration register (ASCR). This
voltage-change sequence consists of the following which are automatically sent by the PWR_I2C unit:
a. Write to the external regulator VCC_APPS DVM Target Voltage 2 register (ADTV2) to set the
VCC_APPS output voltage.
b. Write to the external regulator VCC_SRAM DVM Target Voltage 2 register (SDTV2) to set the
VCC_SRAM output voltage.
c. Write to the Voltage Change Control register (VCC1) to select the ADTV2 and SDTV2 registers for the
voltage settings and enable the voltage change.
Note:
The ADTV2, SDTV2, and VCC1 are registers defined in the power-management integrated
circuit (PMIC) used to interface to the processor.
3. Once the new voltages have been achieved (after the PWR_I
2
C commands are sent and the
PCFR[LPM_DEL] timer expires), the application core PLL is programmed to use the new XL and XN
values.
4. The slave CCU switches the application core clocks to the application core PLL clock outputs.
5. The frequency change sequence exits at the new voltage and frequency.
The following sequence occurs if the programmable module frequency is being increased.
1. The PMU initiates a voltage-change sequence to increase VCC_APPS and VCC_SRAM supplies to the
voltage required by the new programmed frequency settings in the Application Subsystem Clock
Configuration register (ACCR). This voltage-change sequence consists of the following which are
automatically sent by the PWR_I2C unit:
a. Write to the external regulator VCC_APPS DVM Target Voltage 2 register (ADTV2) to set the
VCC_APPS output voltage.
b. Write to the external regulator VCC_SRAM DVM Target Voltage 2 register (SDTV2) to set the
VCC_SRAM output voltage.