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PXA300 Processor and PXA310 Processor 
Vol. I: System and Timer Configuration Developers Manual

                         

Doc. No. MV-TBD-00 Rev. A 

CONFIDENTIAL

 Copyright © 12/13/06 Marvell

Page 200 

Document Classification: Proprietary Information

December 13, 2006

Not approved by Document Control.  For review only.

•

The third sequence in the cascade is the S3 low-power state exit reset sequence. This sequence occurs 
automatically after the hardware-watchdog reset sequence is completed. The MPMU enters the S3 
low-power state exit reset sequence directly with the assertion of the S3 low-power state exit reset.

The SOD, hardware-watchdog reset, and S3 low-power state exit reset sequences are temporary states that are 
exited automatically under the control of the MPMU. 

Figure 3-17

 shows the states used for SOD exit and entry 

to S0 state. 

Figure 3-18

 shows the typical steps taken by the master and subsystem PMUs while initially 

powering up and exiting reset through the cascade sequence to the S0 state. See 

Section 8.6

 for more information 

on individual resets.

Summary of Contents for PXA300

Page 1: ... R V E L L C O N F I D E N T I A L U N D E R N D A 1 2 1 0 1 0 5 0 69rlq62d f714peg4 Memec Headquarters Unique Tech Insight Impact UNDER NDA 12101050 MARVELL CONFIDENTIAL UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED Doc No MV TBD 00 Rev A December 13 2006 Document Classification Proprietary Information Not approved by Document Control For review only PXA300 and PXA310 Processor Vol I Syste...

Page 2: ... or recipient in the absence of appropriate U S government authorization agrees 1 Not to re export or release any such information consisting of technology software or source code controlled for national security reasons by the U S Export Control Regulations EAR to a national of EAR Country Groups D 1 or E 2 2 Not to export the direct product of such technology or such software to EAR Country Grou...

Page 3: ...nt 24 1 2 5 Power I2C Controller 25 1 2 6 One Wire Controller 25 1 2 7 Graphics Controller 26 1 2 8 Performance Monitor 27 1 2 9 Internal Memory Architecture 27 1 2 10 Internal SRAM Memory 27 1 2 11 External Memory Interfaces 27 1 2 12 Dynamic Memory Controller 28 1 2 13 Static Memory Controller 28 1 2 14 Data Flash Controller 29 1 2 15 Interrupt Controller 30 1 2 16 Operating System Timers 30 1 2...

Page 4: ...w 50 2 15 1 Intel XScale Microarchitecture Coprocessor Register Summary 51 2 15 2 Interrupt Controller Registers 53 2 15 3 Performance Monitoring Registers 54 2 15 4 Clock Configuration and Power Management Registers 55 2 15 5 Coprocessor Software Debug Registers 55 2 15 6 Coprocessor 15 56 3 Memory Switch 61 3 1 Overview 61 3 1 1 Differences Between PXA300 Processor and PXA310 Processor 61 3 2 Fe...

Page 5: ...GSRERx and GPIO Bit wise Clear Rising Edge GCRERx Detect Enable Registers 132 5 3 8 GPIO Falling Edge Detect Enable Registers GFERx 134 5 3 9 GPIO Bit Wise Set Falling Edge GSFERx and GPIO Bit wise Clear Falling Edge GCFERx Detect Enable Registers 134 5 3 10 GPIO Edge Detect Status Register GEDRx 136 5 4 Register Summary 137 6 Services Clock Control Unit 141 6 1 Overview 141 6 1 1 Differences betw...

Page 6: ...bsystem Interrupt Control Status Register AICSR 172 7 3 4 D0 Mode Clock Enable Register A D0CKEN_A 173 7 3 5 D0 Mode Clock Enable Register B D0CKEN_B 174 7 3 6 AC 97 Clock Divisor Value Register AC97_DIV 176 7 3 7 Coprocessor 14 Clock 177 7 4 Register Summary 178 8 Services Power Management Unit 179 8 1 Overview 179 8 2 Differences Between the PXA300 Processor and PXA310 Processor 180 8 3 Features...

Page 7: ...ower Management Unit 237 9 1 Overview 237 9 1 1 Differences Between PXA300 Processor and PXA310 Processor 239 9 2 Operation 239 9 2 1 Reset Management 239 9 2 2 Power Management 241 9 2 3 nBATT_FAULT Occurrence 256 9 2 4 Wake Up Detection 256 9 2 5 Other Power Modes 256 9 2 6 Voltage Management 256 9 3 Register Descriptions 256 9 3 1 Application Subsystem Power Status Configuration Register ASCR 2...

Page 8: ...ls 295 11 3 2 DMA Descriptors 297 11 3 3 Transferring Data 302 11 3 4 Programming Tips 304 11 3 5 How DMA Handles Trailing Bytes 305 11 3 6 Quick Reference to DMA Programming 308 11 3 7 Examples 314 11 4 Register Descriptions 319 11 4 1 DMA Request to Channel Map Register DRCMRx 319 11 4 2 DMA Descriptor Address Registers DDADRx 320 11 4 3 DMA Source Address Register DSADRx 321 11 4 4 DMA Target A...

Page 9: ...tch Module 389 13 5 3 Stopwatch Module 394 13 5 4 Periodic Interrupt Module 395 13 5 5 Trimmer Module 396 13 6 Register Descriptions 398 13 6 1 RTC Trim Register RTTR 399 13 6 2 RTC Status Register RTSR 400 13 6 3 RTC Alarm Register RTAR 402 13 6 4 Wristwatch Day Alarm Registers RDARx 403 13 6 5 Wristwatch Year Alarm Registers RYARx 404 13 6 6 Stopwatch Alarm Registers SWARx 405 13 6 7 Periodic In...

Page 10: ... 1 Differences Between the PXA300 Processor and PXA310 Processor 429 15 2 Features 429 15 3 Signal Descriptions 429 15 4 Operation 430 15 4 1 Performance Monitoring 430 15 4 2 PXA300 Processor and PXA310 Processor Level Performance Events 430 15 4 3 Debug Functionality 433 15 5 Register Definitions 434 15 5 1 Event Select Registers PML_ESL_ 7 0 434 15 5 2 PXA300 Processor and PXA310 Processor Debu...

Page 11: ...E R N D A 1 2 1 0 1 0 5 0 69rlq62d f714peg4 Memec Headquarters Unique Tech Insight Impact UNDER NDA 12101050 MARVELL CONFIDENTIAL UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED Copyright 12 13 06 Marvell CONFIDENTIAL Doc No MV TBD 00 Rev A December 13 2006 Document Classification Proprietary Information Page 11 Not approved by Document Control For review only 18 Memory Map 461 18 1 Overview ...

Page 12: ...es 143 8 1 MPMU and BPMU Power States 180 8 2 Subsystem Reset Distribution 186 8 3 Power Domains Connection 197 8 4 Services Unit Power Domains 198 8 5 MPMU and BPMU Power Modes 199 8 6 SOD Power On Master PMU State Sequence 201 8 7 Steps Taken by Master and Subsystem for Initial Power Up and Exit of Reset 202 8 8 S0 13 MHz Clock Enable Sequence 203 8 9 S0 Low Voltage Supply Enable Sequence 204 9 ...

Page 13: ...rocessor Alternate Function Table 75 4 3 PXA300 Processors Signal Descriptions 86 4 4 PXA300 Processor Pad Control Addresses 101 4 5 PXA310 Processor Pad Control Addresses 105 4 6 MFPR Bit Definitions 111 4 7 Low Power Mode States 116 4 8 SLEEP_SEL and RDH Multi function Pin State Summary 117 4 9 Peripheral Controller Wake Ups 118 4 10Generic Wakeups 120 5 1 GPIO Controller Interface Signals Summa...

Page 14: ...locks Register Summary 178 7 18IAS Revision Changes 178 7 18DM Revision Changes 178 8 1 Power Management Unit Pin Definitions 181 8 2 Summary of Module Reset Functions 191 8 3 Summary of Subsystem Dx States 194 8 4 Internal Power Domains 195 8 5 External Power Supplies 195 8 6 PMCR Bit Definitions 222 8 7 PSR Bit Definitions 224 8 8 PSPR Bit Definitions 226 8 9 PCFR Bit Definitions 227 8 10PWER Bi...

Page 15: ...8DMA Quick Reference for On Chip Peripherals 310 11 9DRCMR0 63 DRCMR64 99 Bit Definitions 319 11 10DDADR0 31 Bit Definitions 320 11 11DSADR0 31 Bit Definitions 322 11 12DTADR0 31 Bit Definitions 323 11 13DCMD0 31 Bit Definitions 324 11 14DRQSR0 Bit Definitions 328 11 15DCSR0 31 Bit Definitions 329 11 16DINT Bit Definitions 336 11 17DALGN Bit Definitions 337 11 18DPCSR Bit Definitions 338 11 19DMA ...

Page 16: ... 409 13 17RTC Controller Register Summary 409 14 1Operating System Timers Interface Signals Summary 412 14 2OMCR4 5 6 7 Bit Definitions 417 14 3OMCR8 10 Bit Definitions 418 14 4OMCR9 11 Bit Definitions 421 14 5OSMR0 11 Bit Definitions 423 14 6OWER Bit Definitions 424 14 7OIER Bit Definitions 424 14 8OSCR0 Bit Definitions 425 14 9OSCR4 OSCR11 Bit Definitions 425 14 10OSSR Bit Definitions 426 14 11O...

Page 17: ...0 MARVELL CONFIDENTIAL UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED Copyright 12 13 06 Marvell CONFIDENTIAL Doc No MV TBD 00 Rev A December 13 2006 Document Classification Proprietary Information Page 17 Not approved by Document Control For review only Revision History Date Revision Description March 2004 001 Initial release limited internal distribution March 2005 0 9 Initial release unde...

Page 18: ...I n s i g h t I m p a c t M A R V E L L C O N F I D E N T I A L U N D E R N D A 1 2 1 0 1 0 5 0 69rlq62d f714peg4 Memec Headquarters Unique Tech Insight Impact UNDER NDA 12101050 MARVELL CONFIDENTIAL UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED Copyright 12 13 06 Marvell CONFIDENTIAL Doc No MV TBD 00 Rev A December 13 2006 Document Classification Proprietary Information Page 18 Not approve...

Page 19: ... multiplexing and provides an overview of clocking and power management features This volume also provides detailed information on system wide functions such as the memory switch clock control power management 1 Wire bus DMA controller general purpose I O GPIO controller real time clock operating system timers system bus arbitration and interrupt control Vol II PXA300 Processor and PXA310 Processo...

Page 20: ...is represented as 0x6B in hexadecimal and 0b110_1011 in binary 1 1 2 Naming Conventions All signal and register bit names appear in uppercase Active low items are prefixed with a lowercase n Bits within a signal name are enclosed in angle brackets EXTERNAL_ADDRESS 31 0 nCS 1 Bits within a register bit field are enclosed in square brackets REGISTER_BITFIELD 3 0 REGISTER_BIT 0 In register definition...

Page 21: ...are Developers Guide Intel XScale Core Developers Manual Intel Mobile Scalable Link Specification General information http developer intel com Mobile DDR SDRAM Specification CF and CompactFlash Specification Version 1 4 CompactFlash Association http www compactflash org Bluetooth wireless technology SIG Inc http www bluetooth org I2 C Bus Specification Philips Semiconductors http www phillipssemic...

Page 22: ...PXA310 processor provides the configuration support for two dedicated memory interfaces to support high speed DDR SDRAM VLIO devices and data flash devices This flexibility enables high performance store and download as well as execute in place system architectures The PXA300 processor or PXA310 processor memory architecture features a memory switch that allows multiple simultaneous memory transac...

Page 23: ...RISC technology achieves high speed and ultra low power Dynamic voltage management incorporates voltage and frequency on the fly scaling to allow applications to implement optimal performance and power Media processing technology lets the multiply accumulate coprocessor MAC perform two simultaneous 16 bit single instruction multiple data SIMD multiplies with 40 bit accumulation for efficient media...

Page 24: ...is of hit rates Debug unit uses hardware breakpoints and 256 entry trace history buffer for flow change messages to debug programs 32 bit coprocessor interface provides a high performance interface between core and coprocessors 64 bit core memory bus with simultaneous 32 bit input path and 32 bit output path provides up to 3 2 Gbps 403 MHz bandwidth for internal accesses Eight entry write buffer a...

Page 25: ...programmable I2 C based external regulator interface to power management ICs 1 Wire controller for battery gauge operations See Vol I PXA300 Processor and PXA310 Processor Developers Manual System and Timer Configuration for more details 1 2 5 Power I2 C Controller The PWR I2C controller allows the PWR I2C unit to interface to compatible Power I2C devices attached to the Power I2C bus This control...

Page 26: ...cs Controller This chapter describes the overview requirements functions and architecture for the graphics controller that is inside of the PXA300 processor or PXA310 processor graphics controller The graphics controller features are Graphics instruction list parser Two source buffers Three destination buffers including internal and external display buffers front back buffers Support for multiple ...

Page 27: ...has occurred allowing the software routine to read and accumulate the register contents Counters are accessible using coprocessor 14 on the core 1 2 9 Internal Memory Architecture The PXA300 processor or PXA310 processor memory architecture features a memory switch that allows multiple simultaneous memory transactions between different sources and targets For example the PXA300 processor or PXA310...

Page 28: ...cify bus slew rates and pullup pulldown strengths It provides 16 data lines 16 address lines and several control signals 1 2 12 Dynamic Memory Controller The dynamic memory controller is used for interfacing to DDR SDRAMs The Dynamic memory controller is only connected to the EMPI Key features include One or two partitions of DDR SDRAM running at a maximum of 208 MHz Multiple partitions of DDR SDR...

Page 29: ...essor Developers Manual Memory Controller Configuration for more details 1 2 14 Data Flash Controller The data flash controller is used to manage external data flash memory that is typically used to hold the operating system image and as a non volatile mass storage hard disk drive Key features include Supports third party data flash devices Hardware ECC General features include A D muxed interface...

Page 30: ...er through memory mapped or coprocessor registers Key features include Peripheral interrupt sources can be mapped to normal IRQ or fast FIQ interrupt request Each interrupt source can be independently enabled Priority mechanism to indicate highest to lowest priority interrupts Accessible via the coprocessor interface for fast access Accessible as a memory mapped peripheral for backward compatibili...

Page 31: ...ter 10 bit pulse control See Vol IV PXA300 Processor and PXA310 Processor Developers Manual Serial Controller Configuration for more details 1 2 18 Real Time Clock RTC The real time clock is a 32 bit counter with trim control that runs off of the 32 768 kHz crystal oscillator The general features of the RTC are Timer User programmable free running counter User programmable alarm register Resolutio...

Page 32: ...r Developers Manual System and Timer Configuration for more details 1 2 20 DMA Controller The PXA300 processor or PXA310 processor contains a descriptor based DMA controller The descriptors are stored in memory and are fetched upon receipt of a DMA request from a particular unit The descriptors support looping and branching constructs The DMA controller provides the following key features Supports...

Page 33: ...h speed unidirectional physical link interfaces one inbound and one outbound Links have scalable data channel width options of 4 2 or 1 bits Asynchronous clocking from 0 to 48 MHz per link Transfer rates per link up to 96 Mbps 14 independent logical data channels 7 inbound 7 outbound for managing multiple simultaneous data streams Large 64 byte FIFO buffer for each logical data channel Round robin...

Page 34: ...for communications link fault isolation Break parity overrun and framing error simulation All UARTs can operate in slow infrared SIR IRDA mode All UARTs have hardware flow control support nRTS output controlled by UART receiver FIFO nCTS input from modem controls UART transmitter UART 1 has these additional modem control functions nDSR nDTR nRI nDCD See the Vol IV PXA300 Processor and PXA310 Proce...

Page 35: ...ller Configuration for more details 1 2 22 4 AC 97 CODEC Interface The AC 97 CODEC interface supports these key features Independent channels for stereo pulse code modulated PCM In stereo PCM Out surround PCM out center LFE PCM out MODEM Out MODEM In and mono Mic in The above channels support 16 bit samples only Supports multiple sample rate AC 97 2 3 CODECs 48 kHz and below The AC 97 controller d...

Page 36: ...int data storage See Vol IV PXA300 Processor and PXA310 Processor Developers Manual Serial Controller Configuration for more details 1 2 22 6 USB 1 1 Host Controller The USB host controller has the following key features USB Rev 1 1 compatible Three host ports Supports both low speed and full speed USB devices Open Host Controller Interface OHCI Rev 1 0a compatible Root hub supports 3 chained down...

Page 37: ...Serial Protocol SSP Motorola Serial Peripheral Interface SPI protocol Inter IC Sound I2 S protocol emulated using the PSP protocol See Monahans Processor I2 S Emulation Using SSP PSP Application Note Four SSPs Up to 13 Mbps transfer rate with internal clock generation Packed mode to allow double depth FIFOs if sample less than 16 bits wide Sample data formats from 8 16 18 and 32 bits of serial dat...

Page 38: ...rogrammable to be automatically loaded at the beginning of each frame Command data RAM 16 x 9 bits to hold command data Provides one base layer plus two overlays maximum size of each overlay can equal the display size Integrated seven channel DMA one channel for base plane one channel for overlay 1 three channels for overlay 2 and one channel for the hardware cursor Supports hardware cursor Progra...

Page 39: ... and four bit data transfers are supported in SD and SDIO modes Data transfer clock of 26 MHz Two modes of operation MMC SD SDIO mode and SPI mode MMC SD SDIO mode supports MMC SD and SDIO communication protocols SPI mode supports the SPI communications protocol Controller turns clock on and off based on status of FIFOs to prevent overflows and underruns Dual transmit FIFOs and dual receive FIFOs ...

Page 40: ...scriber ID Controller The PXA300 processor or PXA310 processor provides two Universal Subscriber Identity Module USIM interfaces Each controller provides these key features Compatible with any USIM SmartCard that is compliant with standard ISO 7816 3 and 3G TS 31 101 Supports control lines for two level voltage supply 1 8 V and 3 V Supports USIM SmartCard reset pin control using reset pin control ...

Page 41: ... external synchronization signaling Preprocessed YCbCr 4 2 2 planar capture mode RAW RGGB CMYG capture modes Support for packing of 8 and 10 bit RAW pixel data up to 2560x2048 Pixel processing preview chain supporting up to 1280x1024 resolution SXGA Three programmable 64 element look up tables LUT Three independent mapping functions fR x fG x and fB x supported Companding from 10 bit to 8 bit RAW ...

Page 42: ...has the following features JTAG interface Conforms to the IEEE Std 1149 1 1990 and IEEE Std 1149 1a 1993 Standard Test Access Port and Boundary Scan Architecture Test access port with dedicated pins TDI TMS TCK nTRST and TDO See Vol I PXA300 Processor and PXA310 Processor Developers Manual System and Timer Configuration for more details 1 3 Intel XScale Microarchitecture Compatibility The Intel XS...

Page 43: ... Sophisticated power management Highly multiplexed pin usage 2 0 1 Differences Between PXA300 Processor and PXA310 Processor There are no architectural differences between the PXA300 processor and PXA310 processor except the values of the Processor ID register Refer to Section 2 15 6 1 Processor ID Register for more information on this register 2 1 Intel XScale Microarchitecture Implementation Opt...

Page 44: ...cts directly to the core and to the internal and external memories 2 4 I O Ordering The PXA300 processor or PXA310 processor uses queues that accept memory requests from the seven internal masters System Bus 1 contains the DMA controller USB host LCD controller camera interface and a bridge to the peripheral buses System Bus 2 contains the USB 2 0 Client and 2D graphics controller Operations issue...

Page 45: ...e memory receives or from the memory to the peripheral transmits In case of transmits if the DMA descriptor has a byte count that is not an integer multiple of the transfer size then at the end of the descriptor DMA performs a transfer that is shorter than the transfer size This is the trailing bytes case for transmits On transmits for every peripheral request DMA transfers the number of bytes equ...

Page 46: ...ctions an initial transaction to send the request and a separate data transfer to return the read data During the gap between these two operations the system bus is relinquished and can be used by other devices For a write operation the system bus transaction completes when the write has transferred over to the DMA bridge rather than waiting until it reaches the actual peripheral In both cases ope...

Page 47: ...t case latency for an external memory transfer in a very busy system where all of the internal bus masters are continuously trying to access a system bus assuming that the master has highest priority programmed in the arbiter the following transfers can occur ahead of the current master accessing the external bus and must be accounted for One current external bus transfer Several pending transfers...

Page 48: ...s responsible for servicing the interrupt and clearing it in the source unit before exiting the service routine Note There is a delay between writing to a status bit to clear an interrupt and the interrupt actually being cleared Therefore clear the interrupt early in the interrupt service routine to allow the status bit time to clear before returning from the routine 2 12 Reset The PXA300 processo...

Page 49: ...peripherals are mapped to multiple pins as shown in the pin function descriptions The GPIO function that is the ability to set and read the value on a pin is an alternate function choice among the other alternate functions for a given pin Note Multiple mappings does not mean multiple instances of a peripheral only that the peripheral can be connected to the pins in several ways 2 14 Power On Reset...

Page 50: ...ess map for memory and memory mapped registers It also summarizes the registers within the independent coprocessors in the processor core Refer to individual unit chapters of the peripherals volume for the mapping of individual registers All internal control and configuration registers are mapped in physical memory space on 32 bit address boundaries Use 32 bit word access loads and stores to acces...

Page 51: ...ough memory map addressing Refer to the Intel XScale Core Developers Manual for more information on the coprocessor registers Table 2 3 Coprocessor Register Summary Sheet 1 of 3 CRn CRm Opcode1 Opcode2 Register Symbol Register Description Coprocessor 6 Interrupt Controller 0 0 0 0 ICIP Interrupt Controller IRQ Pending 1 0 0 0 ICMR Interrupt Controller Mask 2 0 0 0 ICLR Interrupt Controller Level 3...

Page 52: ...tion Register 7 0 0 0 PWRMODE Power Mode Coprocessor 14 Software Debug 8 0 0 0 TX Transmit Debug Register 9 0 0 0 RX Receive Debug A 0 0 0 DCSR Debug Control and Status B 0 0 0 TBREG Trace Buffer C 0 0 0 CHKPT0 Checkpoint 0 D 0 0 0 CHKPT1 Checkpoint 1 E 0 0 0 TXRXCTRL Transmit and Receive Control Coprocessor 15 Intel XScale Microprocessor System Control ID and Cache Type Registers 0 0 0 0 ID Ident...

Page 53: ... of two modes 8 7 0 0 Invalidate I D TLB 8 5 0 0 Invalidate I TLB 8 5 0 1 Invalidate I TLB Entry 8 6 0 0 Invalidate D TLB 8 6 0 1 Invalidate D TLB Entry Cache Lock Down 9 1 0 0 Fetch and Lock I Cache Line TLB Operations 9 1 0 1 Unlock I Cache 9 2 0 0 Read Data Cache Lock Register 9 2 0 0 Write Data Cache Lock Register 9 2 0 1 Unlock Data Cache TLB Lock Down 10 4 0 0 Translate and Lock Instruction ...

Page 54: ...errupt control registers via the CP is limited depending whether the core is in user or supervisor mode An undefined instruction exception is generated if an access is made in user mode 2 15 3 Performance Monitoring Registers Access Coprocessor 14 see Table 2 4 The performance monitoring registers include four 32 bit performance counters allowing four separate events to be monitored simultaneously...

Page 55: ...e whole system from an integrated ring oscillator this produces a set of frequencies different from the ones derived from the core and system PLL As the base frequency standard is only accurate to 10 there are inaccuracies on the delivered frequencies In the ring oscillator mode only a subset of the devices are capable of running and with some restrictions Table 2 5 Devices Operating in Ring Oscil...

Page 56: ... 2 15 6 4 Coprocessor Access Register Section 2 15 6 5 Additions to Coprocessor 15 Functionality 2 15 6 1 Processor ID Register Access Coprocessor 15 Register 0 opcode_2 0 Table 2 6 shows the format and values presented in the Processor ID register This read only register is accessible only in supervisor mode It conforms with the values provided in the ARM Architecture Reference Manual Table 2 6 P...

Page 57: ...it Access Coprocessor 15 Register 1 opcode_2 1 Bit 1 of the Auxiliary Control register is defined as the page table memory attribute P bit It is not implemented in the PXA300 processor or PXA310 processor and must be written with 0b0 Similarly the P bit in the memory management unit MMU page table descriptor is not implemented and must be written with 0b0 2 15 6 4 Coprocessor Access Register Acces...

Page 58: ...on 2 15 6 5 2 15 6 5 Additions to Coprocessor 15 Functionality At times it is necessary to know exactly when a CP15 update takes effect For example when enabling memory address translation turning on the MMU it is vital to know when the MMU is actually guaranteed to be in operation To address this need a processor specific code sequence is defined for the Intel XScale core Example 2 2 describes th...

Page 59: ...ROHIBITED System Architecture Overview Copyright 12 13 06 Marvell CONFIDENTIAL Doc No MV TBD 00 Rev A December 13 2006 Document Classification Proprietary Information Page 59 Not approved by Document Control For review only At this point any previous CP15 writes are guaranteed to have taken effect ENDM When setting multiple CP15 registers it is acceptable to execute CPWAIT only once after the sequ...

Page 60: ...R V E L L C O N F I D E N T I A L U N D E R N D A 1 2 1 0 1 0 5 0 69rlq62d f714peg4 Memec Headquarters Unique Tech Insight Impact UNDER NDA 12101050 MARVELL CONFIDENTIAL UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED PXA300 Processor and PXA310 Processor Vol I System and Timer Configuration Developers Manual Doc No MV TBD 00 Rev A CONFIDENTIAL Copyright 12 13 06 Marvell Page 60 Document Clas...

Page 61: ...or a single bus This chapter refers to agents that can initiate new read or write transfers as initiators Similarly the agents that complete those transfers are referred to as completers The completer interface and initiator interface are the logic that connects the completer or initiator to the memory switch bus See Figure 3 1 for a graphic representation of the memory switch bus which separates ...

Page 62: ...terface between the core subsystem and the bus System bus 1 interface The interface between system bus 1 and the bus System bus 2 interface The interface between system bus 2 and the bus Dynamic Memory Controller DMC interface The interface between the DMC and the bus Static Memory Controller SMC interface The interface between the SMC and the bus Internal SRAM interface The interface between inte...

Page 63: ... R N D A 1 2 1 0 1 0 5 0 69rlq62d f714peg4 Memec Headquarters Unique Tech Insight Impact UNDER NDA 12101050 MARVELL CONFIDENTIAL UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED Memory Switch Copyright 12 13 06 Marvell CONFIDENTIAL Doc No MV TBD 00 Rev A December 13 2006 Document Classification Proprietary Information Page 63 Not approved by Document Control For review only Figure 3 1 PXA300 a...

Page 64: ... The Memory Switch Concept The memory switch bus is responsible for handling the read and write address data and related attributes from the initiators to the completers Figure 3 1 illustrates the overall concept of the memory switch bus Figure 3 2 shows only the path from one initiator to one completer though many such paths exist within the memory switch bus The initiators interfacing with the m...

Page 65: ... last driven output value or instead be forced into one of five states output driven high output driven low output high impedance input pulled high and input pulled low This register defaults to an appropriate state at reset or power up but is software configurable thereafter The pin unit also contains registers to configure the output drive strength of individual pins when configured as outputs M...

Page 66: ...Functions Table 4 1 PXA300 Processors Alternate Function Table Pin Name Power Supply Primary Function at Reset Alt FN 0 Alt FN 1 Alt FN 2 Alt FN 3 Alt FN 4 Alt FN 5 Alt FN 6 Alt FN 7 GPIO0 VCC_DF GPIO_0 RDY GPIO1 VCC_DF GPIO_1 nCS 2 GPIO2 VCC_DF GPIO_2 nCS 3 SMEM_DF_XCV REN GPIO3 VCC_CARD1 GPIO_3 U_IO wake ADxER 19 KP_DKIN 6 MM1_DATA 0 Wake GENERIC 10 GPIO4 VCC_CARD1 GPIO_4 U_DETECT wake ADxER 19 ...

Page 67: ...CC_IO3 GPIO_17 PWM 0 SSPSFRM2 EXT_SYNC0 wake GENERIC 12 GPIO18 VCC_IO3 GPIO_18 PWM 1 SSPRXD AC97_SDATA_I N_3 wake GENERIC 0 UART2_TXD UART2_RXD EXT_SYNC1 wake GENERIC 12 SSPTXD1 GPIO19 VCC_IO3 GPIO_19 PWM 2 SSPTXD2 KP_MKOUT 4 UART2_RXD UART2_TXD CHOUT0 SSPRXD2 GPIO20 VCC_IO3 GPIO_20 PWM 3 SSPTXD KP_MKOUT 5 HZ_CLK ONE_WIRE CHOUT1 SSPRXD GPIO21 VCC_IO3 GPIO_21 SCL wake GENERIC 9 GPIO22 VCC_IO3 GPIO_...

Page 68: ...ATAI N2 UART1_CTS UTM_PHYDATA OUT2 UART1_RTS GPIO33 VCC_IO3 GPIO_33 U2D_PHYDATAI N3 UART1_DCD wake GENERIC 3 UTM_PHYDATA OUT3 SSPSCLK SSPSCLK2 GPIO34 VCC_IO3 GPIO_34 U2D_PHYDATAI N4 UART1_DSR wake GENERIC 3 UTM_PHYDATA OUT4 UART1_DTR SSPSFRM SSPSFRM2 GPIO35 VCC_IO3 GPIO_35 U2D_PHYDATAI N5 UART1_RI wake GENERIC 3 UTM_PHYDATA OUT5 SSPRXD SSPTXD SSPRXD2 SSPTXD2 GPIO36 VCC_IO3 GPIO_36 U2D_PHYDATAI N6 ...

Page 69: ...50 GPIO51 VCC_CI CIF_HSYNC U2D_OPMODE0 GPIO 51 GPIO52 VCC_CI CIF_VSYNC U2D_OPMODE1 GPIO 52 GPIO53 VCC_LCD GPIO_53 UTM_TXREADY KP_MKOUT6 GPIO54 VCC_LCD GPIO_54 L_DD 0 SMEM_FADDR4 ML_DD 0 GPIO55 VCC_LCD GPIO_55 L_DD 1 SMEM_FADDR5 ML_DD 1 GPIO56 VCC_LCD GPIO_56 L_DD 2 SMEM_FADDR6 ML_DD 2 GPIO57 VCC_LCD GPIO_57 L_DD 3 SMEM_FADDR7 ML_DD 3 GPIO58 VCC_LCD GPIO_58 L_DD 4 SMEM_FADDR8 ML_DD 4 GPIO59 VCC_LCD...

Page 70: ...RIC 7 GPIO71 VCC_LCD GPIO_71 L_DD 17 SSPRXD3 wake GENERIC 7 KP_MKIN 7 SMEM_FADDR2 1 SSPTXD3 GPIO72 VCC_LCD GPIO_72 L_FCLK_RD SMEM_FADDR2 2 ML_FCLK GPIO73 VCC_LCD GPIO_73 L_LCLK_A0 SMEM_FADDR2 3 ML_LCLK GPIO74 VCC_LCD GPIO_74 L_PCLK_WR SMEM_FADDR2 4 ML_PCLK GPIO75 VCC_LCD GPIO_75 L_BIAS SMEM_FADDR2 5 ML_BIAS GPIO76 VCC_LCD GPIO_76 U2D_RESET L_VSYNC GPIO77 VCC_MSL GPIO_77 UART1_RXD wake GENERIC 3 US...

Page 71: ...L GPIO_86 SSPSFRM wake GENERIC 1 KP_MKOUT 1 KP_DKIN 1 wake ADxER 21 MSL1_IB_DAT 2 Wake ADxER 24 MSL1_OB_DAT 2 GPIO87 VCC_MSL GPIO_87 SSPTXD KP_MKOUT 2 KP_DKIN 2 wake ADxER 21 MSL1_IB_DAT 3 Wake ADxER 24 UTM_RXVALID SSPRXD wake GENERIC 1 MSL1_OB_DAT 3 GPIO88 VCC_MSL GPIO_88 SSPRXD wake GENERIC 1 KP_MKOUT 3 KP_DKIN 3 wake ADxER 21 MSL1_OB_DAT 1 UTM_RXACTIVE SSPTXD MSL1_IB_DAT 1 GPIO89 VCC_MSL GPIO_8...

Page 72: ..._6 U2D_TERM_SE LECT UART1_TXD GPIO100 VCC_IO1 GPIO_100 UART1_TXD USB_P2_6 U2D_RESET USB_P2_2 USB_P2_5 UART1_RXD wake GENERIC 3 KP_MKIN 6 GPIO101 VCC_IO1 GPIO_101 UART1_CTS USB_P2_1 U2D_XCVR_SE LECT UART1_RTS KP_MKIN 7 GPIO102 VCC_IO1 GPIO_102 UART1_DCD wake GENERIC 3 USB_P2_4 UART1_TXD U2D_TERM_SE LECT UART1_RXD wake GENERIC 3 GPIO103 VCC_IO1 GPIO_103 UART1_DSR wake GENERIC 3 USB_P2_8 U2D_SUSPEND ...

Page 73: ... wake GENERIC 4 KP_DKIN 5 wake ADxER 21 UART2_TXD KP_MKIN 6 GPIO113 VCC_IO1 GPIO_113 UART2_TXD KP_DKIN 6 wake ADxER 21 UART2_RXD wake GENERIC 4 KP_MKIN 7 GPIO114 VCC_IO1 GPIO_114 UART2_CTS wake GENERIC 4 KP_DKIN 7 wake ADxER 21 UART2_RTS GPIO115 VCC_IO1 GPIO_115 KP_MKIN 0 wake GENERIC 6 KP_DKIN 0 wake ADxER 21 GPIO116 VCC_IO1 GPIO_116 KP_MKIN 1 wake GENERIC 6 KP_DKIN 1 wake ADxER 21 GPIO117 VCC_IO...

Page 74: ...ght 2006 Marvell Page 4 74 Document Classification Proprietary Information December 13 2006 Preliminary Not approved by Document Control For review only GPIO124 VCC_IO1 GPIO_124 KP_MKOUT 3 KP_DKIN 3 wake ADxER 21 GPIO125 VCC_IO1 GPIO_125 KP_MKOUT 4 KP_DKIN 2 wake ADxER 21 GPIO126 VCC_IO1 GPIO_126 HZ_CLK ONE_WIRE CLK_EXT wake GENERIC 13 KP_MKOUT 7 GPIO127 VCC_IO1 GPIO_127 LCD_CS KP_DKIN 0 GPIO0_2 V...

Page 75: ...0 Processor Pin List with Alternate Functions Table 4 2 PXA310 Processor Alternate Function Table Pin Name Power Supply Primary Function at Reset Alt FN 0 Alt FN 1 Alt FN 2 Alt FN 3 Alt FN 4 Alt FN 5 Alt FN 6 Alt FN 7 GPIO0 VCC_DF GPIO_0 RDY GPIO1 VCC_DF GPIO_1 nCS 2 GPIO2 VCC_DF GPIO_2 nCS 3 SMEM_DF_XCV REN GPIO3 VCC_CARD1 GPIO_3 U_IO wake ADxER 19 KP_DKIN 6 wake ADxER 21 MM1_DATA 0 Wake GENERIC ...

Page 76: ...GPIO_11 SC_CLK KP_MKOUT 5 MM2_DATA 2 wake GENERIC 11 GPIO12 VCC_CARD2 GPIO_12 SC_nRST KP_MKOUT 6 MM2_DATA 3 wake GENERIC 11 GPIO13 VCC_CARD2 GPIO_13 KP_MKOUT 7 MM2_CLK GPIO14 VCC_CARD2 GPIO_14 MM2_CMD Wake GENERIC 11 MM1_CMD Wake GENERIC 10 GPIO15 VCC_CARD2 GPIO_15 SC_VS0 L_CS UART2_CTS wake GENERIC 4 UART2_RTS MM1_CMD Wake GENERIC 10 SSPSCLK wake GENERIC 1 GPIO16 VCC_CARD2 GPIO_16 U_VS0 SSPSFRM w...

Page 77: ...3 VCC_IO3 GPIO_23 AC97_nACRESE T SSPSYSCLK2 MMC_CLK GPIO24 VCC_IO3 GPIO_24 AC97_SYSCLK MMC1_CMD Wake ADxER 26 SSPRXD2 wake GENERIC 2 SSPTXD2 GPIO25 VCC_IO3 GPIO_25 AC97_SDATA_I N_0 Wake GENERIC 0 SSPSCLK2 wake GENERIC 2 GPIO26 VCC_IO3 GPIO_26 SSPSFRM2 wake GENERIC 2 GPIO27 VCC_IO3 GPIO_27 AC97_SDATA_O UT SSPTXD2 SSPRXD2 wake GENERIC 2 GPIO28 VCC_IO3 GPIO_28 AC97_SYNC SSPRXD2 wake GENERIC 2 SSPTXD2...

Page 78: ...GENERIC 2 GPIO34 VCC_ULPI GPIO_34 USB_P2_5 wake ADxER 22 UART1_DSR wake GENERIC 3 ULPI_DATA_OU T4 UART1_DTR SSPSFRM wake GENERIC 1 SSPSFRM2 wake GENERIC 2 GPIO35 VCC_ULPI GPIO_35 USB_P2_3 wake ADxER 22 UART1_RI wake GENERIC 3 ULPI_DATA_OU T5 SSPRXD wake GENERIC 1 SSPTXD SSPRXD2 wake GENERIC 2 SSPTXD2 GPIO36 VCC_ULPI GPIO_36 USB_P2_1 wake ADxER 22 UART1_DTR ULPI_DATA_OU T6 UART1_DSR wake GENERIC 3 ...

Page 79: ..._LCD GPIO_58 L_DD 4 SMEM_FADDR4 ML_DD 4 GPIO59 VCC_LCD GPIO_59 L_DD 5 SMEM_FADDR5 ML_DD 5 GPIO60 VCC_LCD GPIO_60 L_DD 6 SMEM_FADDR6 ML_DD 6 GPIO61 VCC_LCD GPIO_61 L_DD 7 SMEM_FADDR7 ML_DD 7 GPIO62 VCC_LCD GPIO_62 L_DD 8 L_CS SMEM_FADDR8 ML_DD 8 GPIO63 VCC_LCD GPIO_63 L_DD 9 L_VSYNC SMEM_FADDR9 ML_DD 9 GPIO64 VCC_LCD GPIO_64 L_DD 10 SSPSCLK2 wake GENERIC 2 SMEM_FADDR1 0 ML_DD 10 GPIO65 VCC_LCD GPIO...

Page 80: ... L_PCLK_WR SMEM_FADDR2 0 ML_PCLK GPIO75 VCC_LCD GPIO_75 L_BIAS SMEM_FADDR2 1 ML_BIAS GPIO76 VCC_LCD GPIO_76 L_VSYNC GPIO77 VCC_MSL GPIO_77 UART1_RXD wake GENERIC 3 USB_P3_1 wake ADxER 23 UART1_TXD MM2_DATA 0 wake GENERIC 11 MSL1_IB_DAT 0 Wake ADxER 24 MSL1_OB_DAT 0 GPIO78 VCC_MSL GPIO_78 UART1_TXD USB_P3_2 wake ADxER 23 UART1_RXD wake GENERIC 3 MM2_DATA 1 wake GENERIC 11 KP_MKOUT 7 MSL1_OB_CLK KP_...

Page 81: ...O_84 UART1_RTS MM1_DATA 1 Wake GENERIC 10 UART1_CTS wake GENERIC 3 MSL1_OB_WAIT Wake ADxER 24 KP_DKIN 1 wake ADxER 21 MSL1_IB_WAIT GPIO85 VCC_MSL GPIO_85 SSPSCLK wake GENERIC 1 KP_MKOUT 0 KP_DKIN 0 wake ADxER 21 MSL1_IB_DAT 1 Wake ADxER 24 MSL1_OB_DAT 1 GPIO86 VCC_MSL GPIO_86 SSPSFRM wake GENERIC 1 KP_MKOUT 1 KP_DKIN 1 wake ADxER 21 MSL1_IB_DAT 2 Wake ADxER 24 MSL1_OB_DAT 2 GPIO87 VCC_MSL GPIO_87 ...

Page 82: ...7 UART3_RTS UART3_CTS wake GENERIC 5 GPIO93 VCC_IO1 GPIO_93 SSPTXD3 UART3_TXD UART3_RXD wake GENERIC 5 SSPRXD3 wake GENERIC 7 GPIO94 VCC_IO1 GPIO_94 SSPRXD3 wake GENERIC 7 UART3_RXD wake GENERIC 5 UART3_TXD SSPTXD3 GPIO95 VCC_IO1 GPIO_95 SSPSCLK4 wake GENERIC 8 GPIO96 VCC_IO1 GPIO_96 SSPSFRM4 wake GENERIC 8 GPIO97 VCC_IO1 GPIO_97 SSPTXD4 SSPRXD4 wake GENERIC 8 GPIO98 VCC_IO1 GPIO_98 SSPRXD4 wake G...

Page 83: ...VCC_IO1 GPIO_106 UART1_RTS UART1_CTS wake GENERIC 3 GPIO107 VCC_IO1 GPIO_107 UART3_CTS wake GENERIC 5 KP_DKIN 0 wake ADxER 21 UART3_RTS GPIO108 VCC_IO1 GPIO_108 UART3_RTS KP_DKIN 1 wake ADxER 21 UART3_CTS wake GENERIC 5 GPIO109 VCC_IO1 GPIO_109 UART3_TXD KP_DKIN 2 wake ADxER 21 UART3_RXD wake GENERIC 5 GPIO110 VCC_IO1 GPIO_110 UART3_RXD wake GENERIC 5 KP_DKIN 3 wake ADxER 21 UART3_TXD GPIO111 VCC_...

Page 84: ...O1 GPIO_116 KP_MKIN 1 wake GENERIC 6 KP_DKIN 1 wake ADxER 21 GPIO117 VCC_IO1 GPIO_117 KP_MKIN 2 wake GENERIC 6 KP_DKIN 2 wake ADxER 21 GPIO118 VCC_IO1 GPIO_118 KP_MKIN 3 wake GENERIC 6 KP_DKIN 3 wake ADxER 21 GPIO119 VCC_IO1 GPIO_119 KP_MKIN 4 wake GENERIC 6 KP_DKIN 4 wake ADxER 21 GPIO120 VCC_IO1 GPIO_120 KP_MKIN 5 wake GENERIC 6 KP_DKIN 5 wake ADxER 21 GPIO121 VCC_IO1 GPIO_121 KP_MKOUT 0 KP_DKIN...

Page 85: ... Not approved by Document Control For review only GPIO1_2 VCC_IO1 GPIO1_2 USBHPWR KP_DKIN 1 wake ADxER 21 GPIO2_2 VCC_IO3 GPIO2_2 KP_MKIN 6 wake GENERIC 6 KP_MKIN 6 wake GENERIC 6 SSPSFRM wake GENERIC 1 GPIO3_2 VCC_IO3 GPIO3_2 KP_MKIN 7 wake GENERIC 6 KP_MKIN 7 wake GENERIC 6 SSPSFRM wake GENERIC 1 GPIO4_2 VCC_IO3 GPIO4_2 KP_MKOUT 5 KP_DKIN 1 wake ADxER 21 GPIO5_2 VCC_IO3 GPIO5_2 KP_MKOUT 6 KP_DKI...

Page 86: ...ank addressing For static memory accesses these signals provide the upper bits of the address and the lower part of the address is multiplexed on MD 15 0 In this split bus EMPI configuration the EMPI bus is divided into a 16 bit SDRAM bus and a 16 bit static bus Then the MA 15 0 signals are used only for SDRAM addressing and all static address information is multiplexed with the data in one or two...

Page 87: ... and whether the access is to a flash or a static memory device ND_IO 15 0 Bidirectional Third Party data Flash Data Bus Carries data and multiplexed address information for a Third Party data flash and static memory accesses The format of the data and address depends upon the bus configuration and whether the access is to a flash or a static memory device nXCVREN Output Data Flash Transceiver Ena...

Page 88: ... 17 0 Output Low Power Mode LCD Display Data Transfers pixel information from the low power mini LCD controller to the external LCD panel in the S0 D1 low power mode L_CS Output LCD Chip Select Chip select signal for LCD panels with an internal frame buffer L_FCLK_RD Output LCD Frame Clock Frame clock used by the LCD display module to signal the start of a new frame of pixels that resets the line ...

Page 89: ..._TXD Output UART 2 Transmit Data UART2_CTS Input UART 2 Clear to Send UART2_RTS Output UART 2 Request to Send UART3_RXD Input UART 3 Receive Data UART3_TXD Output UART 3 Transmit Data UART3_CTS Input UART 3 Clear to Send UART3_RTS Output UART 3 Request to Send Consumer Infrared Controller Signals CIR_OUT Output Consumer Infrared Output CIR unit output that connects to the IR diode MultiMediaCard S...

Page 90: ...ctional MultiMediaCard Chip Select 1 MMC SD SDIO Controller 2 SD bidirectional line for read and write data Used only for SD 4 bit data transfers SPI chip select 1 MultiMediaCard SD SDIO Controller 3 Signals Important Controller 3 Is An Addition To PXA310 Processor Only MM3_CLK Output MultiMediaCard and SD Card Bus Clock MMC SD SDIO Controller 3 MM3_CMD Bidirectional MultiMediaCard Command MMC SD ...

Page 91: ...t Keypad Direct Key Inputs KP_MKIN 7 0 Input Keypad Matrix Key Inputs KP_MKOUT 7 0 Output Keypad Matrix Key Outputs SSP Signals SSPSCLK Bidirectional Synchronous Serial Port Clock 1 the serial bit clock may be configured as an output master mode operation or an input slave mode operation SSPSFRM Bidirectional Synchronous Serial Port Frame 1 the serial frame sync may be configured as an output mast...

Page 92: ...transceiver interface of a USB client controller as defined by the CFG bits in the USB Port 3 Output Control register UP3OCR USB_P3_2 Bidirectional USB Full Speed Host Port 3 OE output enable signal which connects to an external transceiver or the transceiver interface of a USB client controller as defined by the CFG bits in the USB Port 3 Output Control register UP3OCR USB_P3_3 Bidirectional USB ...

Page 93: ...2 when configured for an external USB OTG transceiver USB Full Speed Transceiver Differential Signals OTG Port 2 and Host Port 1 Important Available On Monahans L Only USBC_P Analog USB Full Speed Client and OTG Port 2 Positive Line this differential signal connects to the USB client interface This signal is routed to the pin named USBOTG_P See note 3 USBC_N Analog USB Full Speed Client and OTG Po...

Page 94: ...SELECT when using boundary scan U2D_SUSPENDM_X Output UTMI Suspend connect to the external UTMI transceiver input that goes low to place the transceiver in a mode that draws minimal power from supplies while retaining the capability for suspend resume operation UTM_LINESTATE 1 0 Input UTMI Line State connect s to the single ended receiver status signals They are asynchronous until a usable CLK is ...

Page 95: ...ds from the Link The PHY will pull ULPI_DIR high whenever the interface cannot accept data from the Link such as during PLL startup ULPI_OTG_INTR Input Interrupt used for for Serial Mode Low Power Mode and Carkit Mode Quick Capture Interface Signals CIF_MCLK Output Quick Capture Interface Master Clock Signal CIF_PCLK Input Quick Capture Interface Pixel Clock Signal CIF_DD 9 0 Input Quick Capture I...

Page 96: ...is an input the default at reset then the two inputs are OR ed and driven to the GPIO input channel Crystal and Clock Signals PXTAL_IN Input Processor Crystal Input can be connected to an external 13 MHz crystal or to an external clock source PXTAL_OUT Analog Processor Crystal Output can be connected to an external 13 MHz crystal or to an external clock source which must be complementary to PXTAL_...

Page 97: ...ntil the power supply is stable and the internal 13 MHz oscillator has stabilized nGPIO_RESET Input GPIO Reset this active low level sensitive input is used to start the processor from the reset vector at address 0 while preserving the contents of memory controller registers Assertion causes the current instruction to terminate abnormally and causes a reset When nRESET is driven high the processor...

Page 98: ...arate variable 1 0 V to 1 4V supply VCC_MVT Power Positive Supply for Internal Logic and I O must be connected to a separate fixed 1 8 V supply VCC_OSC13M Power Positive Supply for 13 MHz Oscillator must be connected to a separate fixed 1 8 V supply VSS_OSC13M Power Ground Reference for 13 MHz Oscillator must be connected to the VSS ground reference VCC_BG Power Positive Supply for Internal Bandga...

Page 99: ... an external 1 8 V 2 5 V 3 0 V or 3 3 V power supply VSS_DF Power Ground for Data Flash Interface must be connected to the ground reference for the VCC_DF supply VCC_MSL Power Positive supply for Mobile Scalable Link must be connected to an external 1 8 V 2 5 V 3 0 V or 3 3 V power supply VSS_MSL Power Ground for Mobile Scalable Link must be connected to the ground reference for the VCC_MSL supply...

Page 100: ...ce driving itself A multi function pin can be programmed to take one of five outputs values resistive pullup nominal 100K resistive pulldown nominal 100K driven high driven low or high impedance Use three state carefully to ensure that no floating node remains on the board at any time These states can be used to form multiple output types for example open collector three state drive etc Note The m...

Page 101: ...of 5 Pin Name Power Supply Pad Control Address DF_IO0 VCC_DF 0x40E1_0220 DF_IO1 VCC_DF 0x40E1_0228 DF_IO2 VCC_DF 0x40E1_0230 DF_IO3 VCC_DF 0x40E1_0238 DF_IO4 VCC_DF 0x40E1_0258 DF_IO5 VCC_DF 0x40E1_0260 DF_IO6 VCC_DF 0x40E1_0268 DF_IO7 VCC_DF 0x40E1_0270 DF_IO8 VCC_DF 0x40E1_0224 DF_IO9 VCC_DF 0x40E1_022C DF_IO10 VCC_DF 0x40E1_0234 DF_IO11 VCC_DF 0x40E1_023C DF_IO12 VCC_DF 0x40E1_025C DF_IO13 VCC_...

Page 102: ...0E1_00BC GPIO3 VCC_CARD1 0x40E1_027C GPIO4 VCC_CARD1 0x40E1_0280 GPIO5 VCC_CARD1 0x40E1_0284 GPIO6 VCC_CARD1 0x40E1_0288 GPIO7 VCC_CARD1 0x40E1_028C GPIO8 VCC_CARD1 0x40E1_0290 GPIO9 VCC_CARD2 0x40E1_0294 GPIO10 VCC_CARD2 0x40E1_0298 GPIO11 VCC_CARD2 0x40E1_029C GPIO12 VCC_CARD2 0x40E1_02A0 GPIO13 VCC_CARD2 0x40E1_02A4 GPIO14 VCC_CARD2 0x40E1_02A8 GPIO15 VCC_CARD2 0x40E1_02AC GPIO16 VCC_CARD2 0x40...

Page 103: ...E1_0430 GPIO40 VCC_CI 0x40E1_0434 GPIO41 VCC_CI 0x40E1_0438 GPIO42 VCC_CI 0x40E1_043C GPIO43 VCC_CI 0x40E1_0440 GPIO44 VCC_CI 0x40E1_0444 GPIO45 VCC_CI 0x40E1_0448 GPIO46 VCC_CI 0x40E1_044C GPIO47 VCC_CI 0x40E1_0450 GPIO48 VCC_CI 0x40E1_0454 GPIO49 VCC_CI 0x40E1_0458 GPIO50 VCC_CI 0x40E1_045C GPIO51 VCC_CI 0x40E1_0460 GPIO52 VCC_CI 0x40E1_0464 GPIO53 VCC_LCD 0x40E1_0468 GPIO54 VCC_LCD 0x40E1_046C ...

Page 104: ..._LCD 0x40E1_04BC GPIO75 VCC_LCD 0x40E1_04C0 GPIO76 VCC_LCD 0x40E1_04C4 GPIO77 VCC_MSL 0x40E1_04C8 GPIO78 VCC_MSL 0x40E1_04CC GPIO79 VCC_MSL 0x40E1_04D0 GPIO80 VCC_MSL 0x40E1_04D4 GPIO81 VCC_MSL 0x40E1_04D8 GPIO82 VCC_MSL 0x40E1_04DC GPIO83 VCC_MSL 0x40E1_04E0 GPIO84 VCC_MSL 0x40E1_04E4 GPIO85 VCC_MSL 0x40E1_04E8 GPIO86 VCC_MSL 0x40E1_04EC GPIO87 VCC_MSL 0x40E1_04F0 GPIO88 VCC_MSL 0x40E1_04F4 GPIO8...

Page 105: ...O112 VCC_IO1 0x40E1_0634 GPIO113 VCC_IO1 0x40E1_0638 GPIO114 VCC_IO1 0x40E1_063C GPIO115 VCC_IO1 0x40E1_0640 GPIO116 VCC_IO1 0x40E1_0644 GPIO117 VCC_IO1 0x40E1_0648 GPIO118 VCC_IO1 0x40E1_064C GPIO119 VCC_IO1 0x40E1_0650 GPIO120 VCC_IO1 0x40E1_0654 GPIO121 VCC_IO1 0x40E1_0658 GPIO122 VCC_IO1 0x40E1_065C GPIO123 VCC_IO1 0x40E1_0660 GPIO124 VCC_IO1 0x40E1_0664 GPIO125 VCC_IO1 0x40E1_0668 GPIO126 VCC...

Page 106: ..._IO7 VCC_DF 0x40E1_0270 DF_IO8 VCC_DF 0x40E1_0224 DF_IO9 VCC_DF 0x40E1_022C DF_IO10 VCC_DF 0x40E1_0234 DF_IO11 VCC_DF 0x40E1_023C DF_IO12 VCC_DF 0x40E1_025C DF_IO13 VCC_DF 0x40E1_0264 DF_IO14 VCC_DF 0x40E1_026C DF_IO15 VCC_DF 0x40E1_0274 DF_CLE_nOE VCC_DF 0x40E1_0240 DF_ALE_nWE VCC_DF 0x40E1_020C DF_SCLK_E VCC_DF 0x40E1_0250 nCS0 VCC_DF 0x40E1_00C4 nCS1 VCC_DF 0x40E1_00C0 nBE0 VCC_DF 0x40E1_0204 n...

Page 107: ...11 VCC_CARD2 0x40E1_029C GPIO12 VCC_CARD2 0x40E1_02A0 GPIO13 VCC_CARD2 0x40E1_02A4 GPIO14 VCC_CARD2 0x40E1_02A8 GPIO15 VCC_CARD2 0x40E1_02AC GPIO16 VCC_CARD2 0x40E1_02B0 GPIO17 VCC_IO3 0x40E1_02B4 GPIO18 VCC_IO3 0x40E1_02B8 GPIO19 VCC_IO3 0x40E1_02BC GPIO20 VCC_IO3 0x40E1_02C0 GPIO21 VCC_IO3 0x40E1_02C4 GPIO22 VCC_IO3 0x40E1_02C8 GPIO23 VCC_IO3 0x40E1_02CC GPIO24 VCC_IO3 0x40E1_02D0 GPIO25 VCC_IO3...

Page 108: ...IO45 VCC_CI 0x40E1_0448 GPIO46 VCC_CI 0x40E1_044C GPIO47 VCC_CI 0x40E1_0450 GPIO48 VCC_CI 0x40E1_0454 GPIO49 VCC_CI 0x40E1_0458 GPIO50 VCC_CI 0x40E1_045C GPIO51 VCC_CI 0x40E1_0460 GPIO52 VCC_CI 0x40E1_0464 GPIO53 VCC_LCD 0x40E1_0468 GPIO54 VCC_LCD 0x40E1_046C GPIO55 VCC_LCD 0x40E1_0470 GPIO56 VCC_LCD 0x40E1_0474 GPIO57 VCC_LCD 0x40E1_0478 GPIO58 VCC_LCD 0x40E1_047C GPIO59 VCC_LCD 0x40E1_0480 GPIO6...

Page 109: ... VCC_MSL 0x40E1_04E0 GPIO84 VCC_MSL 0x40E1_04E4 GPIO85 VCC_MSL 0x40E1_04E8 GPIO86 VCC_MSL 0x40E1_04EC GPIO87 VCC_MSL 0x40E1_04F0 GPIO88 VCC_MSL 0x40E1_04F4 GPIO89 VCC_MSL 0x40E1_04F8 GPIO90 VCC_MSL 0x40E1_04FC GPIO91 VCC_IO1 0x40E1_0500 GPIO92 VCC_IO1 0x40E1_0504 GPIO93 VCC_IO1 0x40E1_0508 GPIO94 VCC_IO1 0x40E1_050C GPIO95 VCC_IO1 0x40E1_0510 GPIO96 VCC_IO1 0x40E1_0514 GPIO97 VCC_IO1 0x40E1_0518 G...

Page 110: ...on December 13 2006 Preliminary Not approved by Document Control For review only 4 7 Register Descriptions Each multi function pin register is identical in structure and definition GPIO116 VCC_IO1 0x40E1_0644 GPIO117 VCC_IO1 0x40E1_0648 GPIO118 VCC_IO1 0x40E1_064C GPIO119 VCC_IO1 0x40E1_0650 GPIO120 VCC_IO1 0x40E1_0654 GPIO121 VCC_IO1 0x40E1_0658 GPIO122 VCC_IO1 0x40E1_065C GPIO123 VCC_IO1 0x40E1_...

Page 111: ...olled by the selected alternate function for the pin 1 The pullup and pulldown resistors are controlled by the PULLUP_EN and PULLDOWN_EN bits in this register overriding the function indicated by the selected alternate function During low power modes this bit is overridden to a 1 and control is thus via the PULLxx_EN bits In these low power states the PULL_SEL bit behaves as a 1 although the regis...

Page 112: ...es of the PULLUP_EN and PULLDOWN_EN bits 6 Read Write EDGE_CLEA R 0 The edge detection logic is enabled and ready to detect an edge 1 The edge detection logic is disabled and no edge will be detected NOTE This is an enable for EDGE_FALL_EN and EDGE_RISE_EN control bits 5 Read Write EDGE_FALL _EN 0 Do not detect a falling edge 1 Detect a falling edge In order to detect a falling edge on this pin se...

Page 113: ...ion of the alternate function connects the pin to its driving logic and that logic is responsible for determining whether the pin is an input or an output For a GPIO function the direction is controlled by the GPIO function that is the direction register For output a pin can be set to drive a 0 1 pull high or pull low or to maintain a three state condition Each option can be selected dynamically a...

Page 114: ...Timer Configuration Developers Manual Doc No MV TBD 00 Rev A CONFIDENTIAL Copyright 2006 Marvell Page 114 Document Classification Proprietary Information December 13 2006 Preliminary Not approved by Document Control For review only Figure 4 1 Pad Module Output Path S1 S8 D C1 ENB C3 C2 Multiplexer S1 S8 D C1 ENB C3 C2 Multiplexer S1 S8 D C1 ENB C3 C2 Multiplexer S1 S8 D C1 ENB C3 C2 Multiplexer S1...

Page 115: ...5 0 69rlq62d f714peg4 Memec Headquarters Unique Tech Insight Impact UNDER NDA 12101050 MARVELL CONFIDENTIAL UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED Copyright 2006 Marvell CONFIDENTIAL Doc No MV TBD 00 Rev A December 13 2006 Preliminary Document Classification Proprietary Information Page 115 Not approved by Document Control For review only Figure 4 2 Pad Module Input Path VCC S1 S8 D ...

Page 116: ...r states to the device and is NOT connected to the edge detection function of the GPIO 4 10 Low Power Mode Operation Low power modes are defined as the state where the internal logical function is not operational but the pin is still required to have a valid value typically the default case This is the case during D1 through D3 modes of operation in D4 mode the actual pins are powered off and no f...

Page 117: ...s in the RDH bit being cleared by hardware and the multi function pin value being determined by the functional unit associated with the multi function pin Transitioning from D3 to D0 results in the multi function pin holding the value shown in Table 4 7 until the RDH bit is cleared by software this holding of the D3 multi function pin value until the RDH bit is cleared is known as delayed release ...

Page 118: ...ster PECR 4 11 2 Peripheral Controller Wakeups There are multiple peripheral controller wakeup events these include functions such as USB client keypad USIM plus others that are described and defined in the Chapter 9 Slave Power Management Unit with detailed register information in Chapter 9 Application Subsystem Wake Up from D3 Enable Register AD3ER through Chapter 9 Application Subsystem Wake Up...

Page 119: ...ey require reading only one register ADxSR to understand what caused the wakeup Example After waking from S2 D3 C4 mode reading the AD3SR register and finding AD3SR WE_GENERIC 5 set indicates that activity on a multi function pin assigned to the SSPSCLK3 SSPSFRM3 or SSPRXD3 alternate functions of the SSP3 controller caused the wakeup event refer to Table 4 10 While it is known that the SSP3 contro...

Page 120: ...p Only the multi function pin assigned to the alternate function serves as a wake up multi function pin For example generic wake up 7 is associated with SSP3 as shown in Table 4 10 The three alternate functions associated with this generic wake up are SSPSCLK3 SSPSFRM3 and SSPRXD3 From Table 4 9 it can be seen that these functions are available on several multi function pins SSPSCLK3 is available ...

Page 121: ...urrently assigned to GPIO89 This same principle applies to the other two alternate functions and their associated GPIO pins There is a workaround to this alternate function assignment requirement being able to use a multi function pin as a wake up Example System software can perform the following to use the GPIO71 pin as a wakeup when SSPRXD3 is not being used in the system Just before entering th...

Page 122: ... L L C O N F I D E N T I A L U N D E R N D A 1 2 1 0 1 0 5 0 69rlq62d f714peg4 Memec Headquarters Unique Tech Insight Impact UNDER NDA 12101050 MARVELL CONFIDENTIAL UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED PXA300 Processor and PXA310 Processor Vol I System and Timer Configuration Developers Manual Doc No MV TBD 00 Rev A CONFIDENTIAL Copyright 2006 Marvell Page 122 Document Classificati...

Page 123: ...Rx The set and clear registers can be written regardless of whether the port is configured as an input or an output If a port is configured as an input the programmed output state takes effect when the port is reconfigured as an output The value of each GPIO port can be read through the GPIO Pin Level register GPLRx This register can be read at any time and can confirm the port state for both inpu...

Page 124: ...ontrol For review only Most external GPIO pins can also serve as either a functional connection or a GPIO port This must be configured through the MFP xx registers and if used for an alternate function overrides the GPIO operation shown in Figure 5 1 All sets of GPIO ports are brought out of the processor and can be multiplexed with any logic function required 5 2 Features The general features of ...

Page 125: ...3 4 GPIO Pin Bit Wise Clear Direction Registers GCDRx on page 5 129 Table 5 1 GPIO Controller Interface Signals Summary Internal Name External Name Type Description GPIO 127 0 Input General Purpose IO Ports The GPIOs are programmable for Inputs or outputs Interrupts or wake up sources Rising or falling edge detection GPIO 17 0 _2 In Out General Purpose IO Ports second instantiation GPIO 17 0 _2 ar...

Page 126: ...write only Modifies value of GRER See Section 5 3 7 GPIO Bit Wise Set Rising Edge GSRERx and GPIO Bit wise Clear Rising Edge GCRERx Detect Enable Registers on page 5 132 12 registers indicate if a falling edge should be detected 4 GFERx read write see Section 5 3 8 GPIO Falling Edge Detect Enable Registers GFERx on page 5 134 4 bit wise set registers GSFERx write only Modifies value of GFER 4 bit ...

Page 127: ...ters GPDRx Users control port direction by programming the GPIO Pin Direction registers GPDR0 GPDR1 GPDR2 and GPDR3 The GPDR registers contain one direction control bit for each of the 128 ports GPDR0 31 0 correspond to GPIO 31 0 GPDR1 31 0 correspond to GPIO 63 32 GPDR2 31 0 correspond to GPIO 95 64 GPDR3 31 0 correspond to GPIO 127 96 If a direction bit is programmed to a 1 the GPIO is an output...

Page 128: ...ion registers GSDR0 GSDR1 GSDR2 and GSDR3 The GSDRx registers contain one direction control bit for each of the 128 ports GSDR0 31 0 correspond to GPIO 31 0 GSDR1 31 0 correspond to GPIO 63 32 GSDR2 31 0 correspond to GPIO 95 64 GSDR3 31 0 correspond to GPIO 127 96 If a direction bit is programmed to a 1 the corresponding bit in GPDRx is set and the GPIO function is configured as an output If it i...

Page 129: ...The GCDR registers contain one direction control bit for each of the 128 pins GCDR0 31 0 correspond to GPIO 31 0 GCDR1 31 0 correspond to GPIO 63 32 GCDR2 31 0 correspond to GPIO 95 64 GCDR3 31 0 correspond to GPIO 127 96 If a direction bit is programmed to a 1 the corresponding bit in GPDR is cleared and the GPIO function is configured as an input If it is programmed to a 0 no change in the GPIO ...

Page 130: ...o the corresponding bit within the GPCRx write only registers reads return unpredictable values Clearing any of the GPSRx or GPCRx bits has no effect on the port state Setting a GPSRx or GPCRx bit corresponding to a port that is configured as an input takes affect only after the port is configured as output The GPSRx and GPCRx registers contain one output set and one output clear control bit respe...

Page 131: ... a status bit is set The GPIO Rising Edge and Falling Edge Detect Enable registers GRERx and GFERx respectively select the type of transition on a GPIO port that causes a bit within the GPIO Edge Detect Enable Status register GEDRx to be set For a given GPIO port its corresponding GRERx bit is set to cause a GEDRx status bit to be set when Table 5 6 GPSR Bit Definitions Physical Address 0x40E0_001...

Page 132: ...pond to GPIO 31 0 GRER1 31 0 correspond to GPIO 63 32 GRER2 31 0 correspond to GPIO 95 64 GRER3 31 0 correspond to GPIO 127 96 Table 5 8 shows the rising edge enable bit locations corresponding to all 32 ports of GRER0 A pair of set clear registers are also provided to enable the setting and clearing of individual bits of the GRERx registers 5 3 7 GPIO Bit Wise Set Rising Edge GSRERx and GPIO Bit ...

Page 133: ...e GPIO functionality or the GRERx register occurs GSRER0 31 0 and GCRER0 31 0 correspond to GPIO 31 0 GSRER1 31 0 and GCRER1 31 0 correspond to GPIO 63 32 GSRER2 31 0 and GCRER2 31 0 correspond to GPIO 95 64 GSRER3 31 0 and GCRER3 31 0 correspond to GPIO 127 96 Table 5 9 shows the bit definitions for GSRER0 and Table 5 10 shows bit definitions for GCRER0 Table 5 9 GSRERx Bit Definitions Physical A...

Page 134: ... transition on a GPIO port that causes a bit within the GPIO Edge Detect Enable Status register GEDRx to be set For a given GPIO port its corresponding GFERx bit is set to cause a GEDRx status bit to be set when the port transitions from logic level high to logic level low Likewise GRERx is used to set the corresponding GEDRx status bit when a transition from logic level low to logic level high oc...

Page 135: ...mmed to a 0 no change in the GPIO functionality or the GFERx register occurs The GCFERx registers contain one detection level clear control bit for each of the 128 ports If a bit is programmed to a 1 the corresponding bit in GFERx is cleared and the GPIO function is configured to NOT cause a GEDRx status bit to be set when the port transitions from logic level one 1 to logic level zero 0 If it is ...

Page 136: ... GEDR0 31 0 correspond to GPIO 31 0 GEDR1 31 0 correspond to GPIO 63 32 GEDR2 31 0 correspond to GPIO 95 64 GEDR3 31 0 correspond to GPIO 127 96 When an edge detect occurs on a port that matches the type of edge programmed in the GRERx and or GFERx registers the corresponding status bit is set in GEDRx Once a GEDRx bit is set the CPU must clear it GEDRx status bits are cleared by writing a 1 to th...

Page 137: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Access Name Description n R Write 1 to clear ED n GPIO edge detect status n where n 0 through 31 0 No edge detect has occurred on the port as specified in GRER and or GFER 1 Edge detect has occurred on the port as specified in GRER and or GFER Table 5 15 GPIO Register Summary Sheet 1 of 3 Nos Address Name Description Page 1 0x40E0_0000 GPLR0 GPIO Pin Level...

Page 138: ...0FC Reserved 30 0x40E0_0100 GPLR3 GPIO Pin Level register GPIO 127 96 126 0x40E0_0104 0x40E0_0108 Reserved 31 0x40E0_010C GPDR3 GPIO Pin Direction register GPIO 127 96 127 0x40E0_0110 0x40E0_0114 Reserved 32 0x40E0_0118 GPSR3 GPIO Pin Output Set register GPIO 127 96 130 0x40E0_011C 0x40E0_0120 Reserved 33 0x40E0_0124 GPCR3 GPIO Pin Output Clear register GPIO 127 96 130 0x40E0_0128 0x40E0_012C Rese...

Page 139: ..._0450 0x40EF_045C Reserved 49 0x40E0_0460 GCRER0 Bit wise Clear of GPIO Rising Edge Detect Enable register GRER 31 0 132 50 0x40E0_0464 GCRER1 Bit wise Clear of GPIO Rising Edge Detect Enable register GRER 63 32 132 51 0x40E0_0468 GCRER2 Bit wise Clear of GPIO Rising Edge Detect Enable register GRER 95 64 132 52 0x40E0_046C GCRER3 Bit wise Clear of GPIO Rising Edge Detect Enable register GRER 127 ...

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Page 141: ...d one or more communication subsystems even though the PXA300 processor or PXA310 processor does not integrate any communications subsystems This architecture partitions power management and clock generation functions into a master controller also known as the services unit and a slave controller within each subsystem The services unit controls the power and clocks for all of the other modules on ...

Page 142: ...ring D0CS mode and power mode startup operation when ACCR PCCE is set 6 1 1 Differences between the PXA300 Processor and PXA310 Processor There are no differences between the PXA300 processor and PXA310 processor in this section 6 2 Features The services clock control unit includes the following features Programmable clock speed frequencies for fast clock speed adjustment of the core clock Program...

Page 143: ...keeping Oscillator Input TXTAL_IN and Timekeeping Oscillator Output TXTAL_OUT TXTAL_IN and TXTAL_OUT are clock I O signals that are used to supply 32 768 kHz clocks to the timekeeping control system TXTAL_IN can be connected to an external 32 768 kHz crystal or an external clock source TXTAL_OUT can be connected to an external 32 768 kHz crystal or ground when an external clock source is connected...

Page 144: ...TCXO Enable VCTCXO_EN VCTCXO_EN signal is asserted to enable an external clock source for the processor oscillator clock VCTCXO_EN is asserted when the services unit CCU is ready to receive the processor oscillator input clock 6 4 Operation 6 4 1 System Clock Requirements The processor oscillator crystal frequency is 13 MHz If an external clock source is used the clock source frequency must be13 M...

Page 145: ...in modes of operation The processor oscillator input can be generated in two ways 1 using an external crystal or 2 an external clock source on the PXTAL_IN pin See Section 6 3 for more information on the clock unit signals used by the processor oscillator For lowest power consumption a 13 MHz crystal must be connected between the PXTAL_IN and PXTAL_OUT pins The external clock source is 13 MHz and ...

Page 146: ...ore and switch logic within the application subsystem Its output is not used within the services unit The core PLL generates two output frequencies one for turbo mode and one for run mode These frequencies are Run mode frequency Processor 13 MHz oscillator XL Turbo mode frequency Run mode frequency XN The valid output frequency selections are shown in Note that the maximum specified frequency for ...

Page 147: ...00 processor or PXA310 processor PMU is in D0 mode the 120 MHz ring oscillator is enabled to output the 120 MHz clock Refer to the Slave Power Management Unit specification for more information on the processor PMU power modes The output frequency of the 120 MHz ring oscillator is not guaranteed has 15 tolerance and cannot be used for peripherals that require a stable consistent clock source Conse...

Page 148: ...XOST Bits Access Name Description 31 22 Reserved Reserved 21 20 R W TSEL Temperature Sensor Throttle Trigger Select 00 100o C 01 90o C 10 95o C 11 105o C 19 17 Reserved Reserved 16 R W TD Frequency Change due to Temperature Condition Disable 0 The core PLL frequency is not automatically changed when there is an on die temperature condition 1 The core PLL frequency is automatically reduced where th...

Page 149: ...ocument Control For review only 6 6 Register Summary Table 6 4 shows the registers associated with the services unit clock control unit and the physical addresses used to access them 7 0 R W VCXOST Determines the wait time for processor oscillator stabilization 0x0 Wait time one 13 MHz clock cycle 0x1 Wait time two 13 MHz clock cycles 0xE5 Wait time 230 13 MHz clock cycles 0xE6 Reserved 0xFF Reser...

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Page 151: ...ed loop 624 MHz Creates the fixed frequency clocks for the high speed I O HSIO bus and low speed I O LSIO bus clocks for the peripheral units in the processor Ring oscillator 120 MHz 15 Creates the fixed frequency clocks used during S0 D0 mode if selected S3 low power reset exit if enabled and power mode startup operation if enabled There are no differences between the PXA300 processor or PXA310 p...

Page 152: ... speed I O clock frequency can be 208 156 or 104 MHz The low speed I O LSIO bus clock is a fixed frequency 26 MHz The low speed I O bus clock is derived from the system PLL clock 7 2 2 Core Phase Locked Loop 104 624 MHz The core PLL is the clock source for the core when in D0 power mode The core PLL generates two output frequencies one for the turbo mode clock run mode frequency XN and one for the...

Page 153: ... Controller ACCR DMCFS Static Memory Controller ACCR SMCFS DF SCLK MEMCLKCFG DF_CLKDIV Data Flash Controller not programmable Video Accelerator Unit Ring Oscillator 60 60 60 60 60 30 15 15 30 60 8 1 104 104 104 104 104 260 78 19 5 156 78 16 1 208 208 104 104 156 260 104 52 156 78 16 2 416 208 156 156 208 260 104 52 156 104 24 2 624 312 208 208 312 260 208 52 156 156 NOTES Frequencies shown in this...

Page 154: ...cations The core PLL is enabled when the processor is in D0 power mode and is disabled when the processor is in D1 D2 D3 or D4 power modes so no clocks are provided in these power modes 7 2 2 1 Turbo Run Mode Note This definition of turbo vs run for PXA300 processor or PXA310 processor is different from the one used in previous generations of Intel XScale processors Specifically for PXA300 process...

Page 155: ...required before switching frequencies with respect to any modules using these clocks 7 2 2 2 Core Frequency Change The core can change frequency by changing the core PLL frequency The core PLL frequency can be adjusted by writing XL and or XN in the Application Subsystem Clock Configuration Register ACCR prior to writing the F bit in the Application Core Clock Configuration Register XCLKCFG When t...

Page 156: ...rformed automatically by hardware in a given mode of operation For programmable clocks such as the HSIO and DDR the selection is performed by writing to the appropriate fields in the Application Subsystem Clock Configuration Register ACCR 7 2 4 Ring Oscillator 120 MHz 15 The ring oscillator outputs a nominal 120 MHz clock 15 and can be the clock source for several peripherals if enabled in the fol...

Page 157: ...bled and powered down When the processor exits the power mode where the core PLL was powered down the BCCU optionally provides the core with clocks from Module Function Internal SRAM Normal operation Dynamic MEMC Recalibration of delay lines is required on exit from D0CS mode This recalibration process is completed automatically by the dynamic memory controller hardware but the recalibration featu...

Page 158: ...cked and stable the processor clocks are started with the PLL outputs In this case no software intervention is necessary or possible given the absence of clocks For a low power mode exit with PCCE 1 software has the option of not switching the clocks over to PLLs and continuing to run off the ring oscillator While operating in this mode it is entirely legitimate for software to issue a second low ...

Page 159: ...Clock Select D0CS bit in the Application Subsystem Clock Configuration Register ACCR register to 0 Write 0x5 to the lower three bits of Section 7 5 16 Application Core PWRMODE Register CP14 Register 7 on page 7 61 The BPMU performs a full system drain as it would for a normal power mode entry and then transitions the system clocks to the PLL based frequencies Warning The part may hang in an unreco...

Page 160: ...oftware must poll the corresponding status update fields in Section 7 3 2 Application Subsystem Clock Status Register ACSR register to determine when the frequency change process has completed 7 2 5 Ring Oscillator 40 MHz 5 During D1 Mode When running in D1 mode the processor uses the 40 MHz ring oscillator as the primary clock source In D1 mode only the mini LCD and SRAM controller are operationa...

Page 161: ...updated before proceeding further Warning When user changes frequency for two or more modules at same time all frequencies have to change in the same direction or stay the same 7 2 8 Changing PLL State The ACCR register contains controls for enabling and disabling the core and system PLLs Specifically these are ACCR XPDIS and ACCR SPDIS They are meant for saving power when the clocks on chip are b...

Page 162: ...he core stores are sent to the system bus This latency varies depending on the number and destination of the stores Note When the core enters idle mode the core PLL continues to operate If the core was operating from the core PLL before entering idle mode the core clock continues to be provided by the core PLL when exiting idle mode After the assertion of an idle mode wake up event the core clocks...

Page 163: ...ly to writing values to purely data fields such as the L and N fields Purely data fields require additional operation before they can be used for example a write to the coprocessor CLKCFG register Finally software must refrain from initiating actions over any coprocessor interface while ACCR initiated operations are in progress Thus a core turbo change can not be initiated while a DMC frequency ch...

Page 164: ...fore software can set PCCE 1 for the next low power mode entry DMC Frequency Select DMCFS Selects the frequency of the dynamic memory controller DMEMC Note 1 The DMEMC gets two clocks from the clocks unit one of which is half the frequency of the other The slower one is sent to the DDR memory chip while the faster is used by the controller itself The frequencies controlled by this field refer to t...

Page 165: ... 3 2 for a description of when each bit in the Application Subsystem Clock Configuration Register ACCR is updated in the Application Subsystem Clock Status Register ACSR The actual value configured in the device is reflected in the Application Subsystem Clock Status Register ACSR see Section 7 3 2 When enabled the critical frequencies are as follows Core turbo mode frequency processor 13 MHz oscil...

Page 166: ...are only available in the PXA300 or PXA310 processor 0b00 104 MHz 0b01 156MHz 0b10 208 MHz 0b11 78 MHz 27 Reserved 26 R W D0CS D0 Mode Clock Select 0 Use the core PLL and system PLLs as the processor clock sources in D0 mode 1 Use the ring oscillator as the processor clock source in D0 mode NOTE Must not be cleared until after an interrupt has been generated indicating that the PLLs are locked or ...

Page 167: ... MHz clock from system PLL provided to application core 0b01 reserved 0b10 reserved 0b11 No clock to core until core PLL is re locked 15 14 R W HSS HSIO Bus Clock Frequency Select Selects the nominal HSIO bus clock frequency 0b00 104 MHz 0b01 156 MHz 0b10 Reserved 0b11 Reserved 13 12 R W DMCFS DDR Memory Controller Clock Frequency Select Selects the frequency of the dynamic memory controller DMEMC...

Page 168: ...rocessor clock source when transitioning from low power mode to D0 mode 10 8 R W XN Core PLL Turbo Mode to Run Mode Ratio Creates the nominal core PLL turbo mode frequency by multiplying the run mode frequency by XN core PLL turbo mode frequency is 13 MHz XL XN NOTE The value of XN must always be less than or equal to the value of the MTS field in the Application Subsystem Power Status Configurati...

Page 169: ...m any power mode or core or system PLL status change The bits map functionally to the corresponding bits in the Application Subsystem Clock Configuration Register ACCR with the addition of Core PLL lock XPLCK Indicates whether the core PLL is ready to use System PLL lock SPLCK Indicates whether the system PLL is ready to use Ring Oscillator Status RO_S Indicates whether the ring oscillator is curr...

Page 170: ... reserved RO_S SMC_S reserved SFL_S XSPCLK_S HSS_S DMC_S reserved XN_S reserved XL_S Reset 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 1 0 0 0 Bits Access Name Description 31 R XPDIS_S Core PLL Output Disable XPDIS Status 0 Core PLL is enabled and output can be used 1 Core PLL is not enabled for use 30 R SPDIS_S System PLL Output Disable SPDIS Status 0 System PLL is enabled and output can be used 1 Sy...

Page 171: ...tem PLL due to an ongoing frequency change 0b01 reserved 0b10 reserved 0b11 Core is currently NOT using the system PLL as the source for its clocks 15 14 R HSS_S HSIO Frequency Select Status 0b00 When the HSIO is clocked by the system PLL the HSIO clock is 104 MHz 0b01 When the HSIO is clocked by the system PLL the HSIO clock is 156 MHz 0b10 When the HSIO is clocked by the system PLL the HSIO cloc...

Page 172: ...ar PCIS Power Mode Change Induced Frequency Change Interrupt Status 0 The core clock is not ready to be switched over to core PLL following a power mode change or AICSR 4 is not set 1 The core clock is ready to be switched over to the core PLL following a power mode change and AICSR 4 is set Note Only set when ACCR PCCE is set 4 R W PCIE Power Mode Change Induced Frequency Change Interrupt Enable ...

Page 173: ... a read write register Ignore reads from reserved bits Write 0b1 to reserved bits Table 7 10 D0CKEN_A Bit Definitions Clock Enable Mappings for Units Physical Address 4134_000C D0CKEN_A BCCU User Settings Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SETALWAYS CKEN 30 CKEN 29 CKEN 28 CKEN 27 CKEN 26 SETALWAYS CKEN 24 CKEN 23 CKEN 22 CKEN 21 CKEN 20 SETAL...

Page 174: ...egister The functionality is absolutely identical to its A counterpart This is a read write register Ignore reads from reserved bits Write 0b1 to reserved bits CKEN 21 UART2 Clock Enable CKEN 5 Monahans LV Processor MMC3 Clock Enable CKEN 5 Monahans L Processor SETALWAYS Must be programmed with 0b1 CKEN 20 UDC Clock Enable CKEN 4 NAND Flash Controller Clock Enable CKEN 19 SETALWAYS Must be program...

Page 175: ... programmed with 0b1 CKEN 15 SETALWAYS Must be programmed with 0b1 CKEN 30 SETALWAYS Must be programmed with 0b1 CKEN 14 SETALWAYS Must be programmed with 0b1 CKEN 29 SETALWAYS Must be programmed with 0b1 CKEN 13 SETALWAYS Must be programmed with 0b1 CKEN 28 SETALWAYS Must be programmed with 0b1 CKEN 12 SETALWAYS Must be programmed with 0b1 CKEN 27 SETALWAYS Must be programmed with 0b1 CKEN 11 Mon...

Page 176: ...ional modes of operation The LSIO clock can be turned off by hardware as a power saving feature based on the rule of clustering Units on the LSIO bus are grouped into clusters Typically a cluster contains multiple units that are identical or similar in function and design A unit can be classified as a cluster all by itself if it is truly one of a kind The clocking rule for clusters is thus when th...

Page 177: ...XA300 processor CP14 register 6 XCLKCFG register The instruction requires the following field assignments Opcode1 0 Opcode2 0 CRn 6 CRm 0 Consult the ARM Reference Manual for details Note CP14 registers can be accessed in supervisor mode only 7 3 7 1 Core Clock Configuration Register XCLKCFG The XCLKCFG register defined in Table 7 16 controls the following modes and sequences Turbo mode See Sectio...

Page 178: ...cessor address Refer to Table 7 17 for the physical address of the memory mapped registers Refer to Table 7 18 for the coprocessor address of the Core Clock Configuration Register Table 7 16 XCLKCFG Bit Definitions Coprocessor 14 Register CR6 XCLKCFG BCCU Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved F T Reset 0 0 Bits Access Name Description 31...

Page 179: ...ement architecture The four MPMU power states include S0 State All internal power domains and external power supplies may be fully powered and functional In this mode all internal clocks may be running The application subsystem may be placed in D0 D1 or D2 power modes and is controlled by the BPMU S1 State Not defined S2 State Entry into S2 state must be coordinated with the BPMU Most internal pow...

Page 180: ...e required external power connections and the internal power domains Each external power supply has an internal power detection circuit referred to as the power on reset for the supply POR The required external power supplies VCC_BBATT VCC_MVT VCC_PLL VCC_BG VCC_APPS VCC_SRAM VCC_OSC13M VCC_MEM VCC_DF VCC_MSL VCC_CI VCC_LCD VCC_CARD1 VCC_CARD2 VCC_USB PXA300 Processor VCC_ULPI PXA310 processor VCC...

Page 181: ...e I O Type Definition nRESET Input An active low input that signals the Tavor device to enter hardware reset state nRESET_OUT Output An active low output that signals the system that the MPMU is in any reset state configurable for S2 S3 and for GPIO reset nGPIO_RESET Input An active low input that signals a soft reset used to reset the device while retaining memory state The application subsystem ...

Page 182: ... is asserted by the MPMU during the initial power up and reset sequences If the SL_ROD bit in the Power Management Unit General Configuration Register PCFR is clear the nRESET_OUT pin is also asserted during S2 and S3 states If the GP_ROD bit in the Power Management Unit General Configuration Register PCFR is clear the nRESET_OUT pin is also asserted during GPIO reset Note nRESET_OUT is deasserted...

Page 183: ... entry is complete when the PWR_EN signal has been de asserted Similarly the EXT_WAKEUP 1 0 signals are not detected as a wake up from S3 state until after S3 state has been entered S3 state entry is complete when the SYS_EN signal is de asserted 8 4 5 Battery Fault nBATT_FAULT The nBATT_FAULT signal is an active low input that tells the MPMU that the main battery is low or has been removed from t...

Page 184: ... VCC_IO1 and VCC_IO3 can be removed Note The low voltage power supplies VCC_APPS and VCC_SRAM are controlled via I2 C commands or PWR_EN and if not disabled prior to SYS_EN being de asserted must be disabled by the de assertion of SYS_EN All low voltage power supplies must be removed before removing any high voltage power supply 8 4 7 Power Enable PWR_EN The PWR_EN signal is an active high output ...

Page 185: ...be optimized for particular applications To provide the above functions the MPMU contains these sections Reset management Power management Voltage management Each part of the MPMU is described in the sections that follow 8 6 Reset Management Operation Reset of the services unit can occur by one of five resets Power on reset An uncompromised ungated total and complete reset used when the VCC_BBATT ...

Page 186: ...herefore references to hardware reset in other chapters must be interpreted as hardware or power on reset See Section 8 7 2 1 for detailed information on power on reset 8 6 1 1 Behavior During Power On Reset During power on reset all internal power domains except the PD_REG PD_DPAD and PD_RTC domains remain powered down see Section 8 7 All internal registers and processes are held at their defined...

Page 187: ...ined reset conditions The core software must examine the Application Subsystem Reset Status register ARSR to determine the reset source 8 6 2 Hardware Reset Hardware reset is invoked when the nRESET pin is asserted and all units are reset to a known state Hardware reset is intended for complete and total reset purposes only 8 6 2 1 Behavior During Hardware Reset During hardware reset all internal ...

Page 188: ...hat allows users to reset the processor while maintaining data in external memory devices and the real time clock GPIO reset is invoked when the nGPIO_RESET pin is asserted low or when SWGR in the Power Management Unit Control Register PMCR is set to 1 GPIO reset does not reset most of the services unit and does not reset the If nBATT_FAULT is asserted while GPIO reset is asserted and PCMR BIE 0 t...

Page 189: ...oked nRESET_OUT is asserted if the GP_ROD bit in the Power Management Unit General Configuration Register PCFR register is clear If nGPIO_RESET is asserted for less than the specified amount of time the detection of the assertion of nGPIO_RESET is indeterminate and as such the processor subsystems may remain in their previous mode or may enter GPIO reset If the MPMU is in S0 state and the BPMU is ...

Page 190: ...sor and PXA310 Processor Electrical Mechanical and Thermal Specification Normal boot up sequencing begins with all units in the processor subsystems starting with their predefined reset conditions except those listed in Table 8 2 The application core software must examine the Application Subsystem Reset Status register ARSR to determine that the reset source was a GPIO reset When the MPMU is in S3...

Page 191: ... D2 C2 S2 D3 C4 or S3 D4 C4 When this event occurs watchdog reset is entered regardless of the previous mode When watchdog reset is invoked the entire processor reset is asserted except to the units as shown in Table 8 2 resetting the services unit application subsystem and the pad unit Additionally all pins assume their reset states including SYS_EN which is negated The sequence for watchdog rese...

Page 192: ...nd power on reset for BBATT is detected The DC DC regulator enables and powers up the services unit dedicated pads timekeeping oscillator MPMU RTC and test logic modules The MPMU asserts nRESET_OUT The timekeeping oscillator enables The MPMU waits for nBATT_FAULT and nRESET to be de asserted The MPMU asserts SYS_EN The external voltage regulators supply VCC_MVT first followed by VCC_PLL VCC_BG VCC...

Page 193: ... PMU BPMU The MPMU controls MPMU Services unit power domains Processor PMU power domain BPMU and services unit resets PMIC I2C interface control of external supplies The BPMU controls All subsystem power domains except the power domain for the slave PMU and timer Subsystem reset sequence except for reset of the BPMU Subsystem wake up events and power mode transitions for D0 D1 D2 power modes The p...

Page 194: ... directing all high voltage supplies to be powered off Off In the off state all power supplies are powered down The off state is exited when VCC_BBATT is applied At beginning of start of day SOD sequence see Section 8 7 2 1 1 Reset Sequences for more information all internal power domains except for the DC DC regulator are powered down all clocks are not functional and all resets are asserted The ...

Page 195: ...Domains Power Domain Associated Module Junction Voltage Range V Generation PD_REG DC DC regulator 2 4 4 0 VCC_BBATT PD_RTC RTC MPMU 32 kHz oscillator and S3 I O logic 1 55 2 0 Output from DC DC converter PD_PLL System and corePLLs 1 55 2 0 VCC_PLL PD_SPMU 13 MHz and ring oscillators 13 MHz PMU PM I2 C and temperature sensor 1 7 1 9 VCC_MVT PD_PMVT I O pad and test units 1 7 1 9 VCC_MVT PD_DPAD Ser...

Page 196: ...A300 Processor and PXA310 Processor Vol I System and Timer Configuration Developers Manual Doc No MV TBD 00 Rev A CONFIDENTIAL Copyright 12 13 06 Marvell Page 196 Document Classification Proprietary Information December 13 2006 Not approved by Document Control For review only VCC_MEM PD_PAD 1 8 SYS_EN VCC_USB PXA300 Processor PD_PAD 3 3 SYS_EN VCC_ULPI PXA310 processor PD_PAD 1 8 SYS_EN VCC_BIAS P...

Page 197: ...mpact UNDER NDA 12101050 MARVELL CONFIDENTIAL UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED Services Power Management Unit Copyright 12 13 06 Marvell CONFIDENTIAL Doc No MV TBD 00 Rev A December 13 2006 Document Classification Proprietary Information Page 197 Not approved by Document Control For review only Figure 8 3 Power Domains Connection Schottky MonahansProcessor PMIC VccSRAM DynamicL...

Page 198: ...TRIBUTION OR USE STRICTLY PROHIBITED PXA300 Processor and PXA310 Processor Vol I System and Timer Configuration Developers Manual Doc No MV TBD 00 Rev A CONFIDENTIAL Copyright 12 13 06 Marvell Page 198 Document Classification Proprietary Information December 13 2006 Not approved by Document Control For review only 8 7 1 1 Application Subsystem Power Domains Figure 8 4 Services Unit Power Domains A...

Page 199: ...ower off state when all power is removed and requires a complete boot to recover In this state all power to the device is off including the backup battery power From the power off state the device goes through the start of day SOD sequence 8 7 2 1 1 Reset Sequences There are three reset sequences for the MPMU which cascade to form the entry to S0 state sequence MPMU entry into the sequences is con...

Page 200: ...rvell Page 200 Document Classification Proprietary Information December 13 2006 Not approved by Document Control For review only The third sequence in the cascade is the S3 low power state exit reset sequence This sequence occurs automatically after the hardware watchdog reset sequence is completed The MPMU enters the S3 low power state exit reset sequence directly with the assertion of the S3 low...

Page 201: ...and pad unit firewalls asserted Initial Power Up Enable low voltage supplies Wakeup while nBATT_FAULT asserted Wakeup while nBATT_FAULT deasserted Count Down SYS_DEL S3 S3 with nBATT_FAULT Enable Clock Reset Wakeup asserted and nBATT_FAULT negated Timekeeping oscillator clock is ok Wakeup asserted and nBATT_FAULT negated nBATT_FAULT asserted nBATT_FAULT negated Wakeup asserted and nBATT_FAULT asse...

Page 202: ... by Master and Subsystem for Initial Power Up and Exit of Reset VCC_BBATT turned on DC DC enabled nRESET_OUT asserted SYS_EN negated MPMU powered on TRST deasserted 32 kHz oscillator enabled Internal resets asserted nBATT_FAULT deasserted nRESET deasserted SYS_EN asserted VCC_MVT VCC_PLL VCC_IOX VCC_MEM VCC_LCD VCC_CARD1 VCC_CARD2 VCC_USB and VCC_MSL turned on Correct voltage or SYS_DEL time expir...

Page 203: ... D1 or D2 When entering S0 state the MPMU de asserts the reset to the BPMU only In S0 state the MPMU provides the processor oscillator ring oscillator PLLs and I2 C voltage manager commands as needed by the subsystem When in S0 state BPMU requests each of the services unit modules when needed Figure 8 8 shows the sequence used by the BPMU to request the 13 MHz oscillator A similar sequence is used...

Page 204: ...ance to S3 state by writing the core PWRMODE register CP14 Register 7 Entrance into any power state other than S3 after receiving the nBATT_FAULT interrupt is not allowed The core must enter S3 state after receiving the nBATT_FAULT interrupt If nBATT_FAULT assertion is detected and the BIE bit in the Power Management Unit Control Register PMCR is set to 0 the MPMU enters S3 state through hardware ...

Page 205: ...initiate the MPMU S2 entry Note When the PWRMODE register CP14 Register 7 is written to initiate MPMU S2 entry the BPMU is transitioned automatically to D3 state prior to MPMU S2 entry For the MPMU to exit S2 due to a S2 wake up event the wake up events must be enabled in both the Power Manager Wake Up Enable Register PWER and Chapter 9 Application Subsystem Wake Up from D3 Enable Register AD3ER 8...

Page 206: ...ogrammed by software prior to entering S2 state and sent to the master and slave PMUs Rising and falling edge transitions are detected on the GPIOs using asynchronous edge detection logic The wake up signals must be held for a specified amount of time for the edge to be detected However the receiving PMU takes up to a specified amount of time to acknowledge the GPIO wake up edge and to begin the w...

Page 207: ...e The ADTV1 SDTV1 VCC1 and OVER1 are registers defined in the power management integrated circuit PMIC used to interface to the processor 4 The MPMU waits the number of timekeeping oscillator cycles specified by the PWR_DEL bits in the Power Management Unit General Configuration Register PCFR 5 The MPMU signals the BPMU that S2 exit has completed and the BPMU can begin to transition the applicatio...

Page 208: ...st units and can be entered either through software control or through the assertion of nBATT_FAULT with PCMR BIE 0 The penalty for this low power mode is that all state is lost and there is no activity inside the application subsystems If the external power supplies are powered down all state may be lost in external devices too There is no activity inside the services unit except for the real tim...

Page 209: ...trol Register PMCR is set If the PCMR BIE bit is set an assertion of nBATT_FAULT causes an interrupt If the PCMR BIE bit is clear an assertion of the nBATT_FAULT causes an automatic entry into S3 state Typically the interrupt handler routine preserves critical application core cache and other critical information before writing the application core PWRMODE register CP14 Register 7 Depending on the...

Page 210: ... VCC_ULPI PXA310 processor VCC_IO1 and VCC_IO3 If any of these supplies is disabled then VCC_APPS must also be disabled 8 7 2 4 8 Entering S3 State Due to nBATT_FAULT Assertion If the PCMR BIE bit is set when nBATT_FAULT is asserted and the BPMU is in run mode an interrupt is signaled to the application core and S3 state is entered by writing the mode bits in the application core PWRMODE register ...

Page 211: ...rough software control Rising and falling edge transitions are detected on the external wake ups using asynchronous edge detection logic The wake up signals must be held for a specified amount of time for the edge to be detected However the receiving PMU takes up to a specified amount of time to acknowledge the external wake up edge and to begin the wake up sequence Refer to the PXA300 Processor a...

Page 212: ...put Voltage Enable register 1 OVER1 to enable the VCC_APPS and VCC_SRAM output voltages Note The ADTV1 SDTV1 and OVER1 registers are defined in the power management integrated circuit PMIC used to interface to the processor 3 The MPMU waits the number of timekeeping oscillator cycles specified by the PWR_DEL bits in the Power Management Unit General Configuration Register PCFR If the SWDD bit in t...

Page 213: ...s operation down to a VCC_BBATT input voltage of 2 4 V and is expected to be used if the VCC_BBATT is configured as a supercap The DC DC converter enables operation down to a VCC_BBATT input voltage of 2 4 V and is expected to be used in systems that do not use a supercap to power VCC_BBATT The DC DC converter is more efficient than the L0 regulator and should be used whenever possible The L0 regu...

Page 214: ...re frequency changes power mode changes and changes due to high temperature When the PWR_I2 C is sending commands the VCSA bit in the Power Management Unit Voltage Change Control Register PVCR is set and the PWR_I2C registers are not writable and read unknown values Software checks the VCSA bit before reading or writing the PWR_I2 C and reads registers following a write to ensure that the read occ...

Page 215: ...nly apps voltage is changed 0x3E is sent if only comms voltage changed 8 8 3 1 Start of Day SOD Operation The PWR_I2 C and voltage change sequencer are used to enable and initially configure the power supplies when triggered during the SOD sequence The MPMU controls the activation of the PWR_I2 C during the SOD sequence When triggered the PWR_I2C sends hard coded commands to set the output voltage...

Page 216: ...Configuration register ASCR and the FVE bit in the Power Management Unit Voltage Change Control Register PVCR Note When raising the application subsystem peripheral frequencies the voltage must be raised first and then the clock switched to the selected higher frequency Conversely when lowering the application subsystem peripheral frequencies the clock must first be switched to the new lower frequ...

Page 217: ...ks to the system PLL Otherwise the application core clocks are disabled 2 The PMU initiates a voltage change sequence to increase VCC_APPS and VCC_SRAM supplies to the voltage required by the new XL and XN settings in the Application Subsystem Clock Configuration register ACCR and MTS settings in the Application Subsystem Power Status Configuration register ASCR This voltage change sequence consis...

Page 218: ...new XL and XN values 3 The PWR_I2C initiates a voltage change sequence to decrease VCC_APPS and VCC_SRAM to the voltages required by the new XL XN and MTS settings Note that the VCC_SRAM supply is not set to a voltage lower than the highest voltage required by the application subsystem The voltage change sequence consists of the following which are automatically sent by the PWR_I2C unit a Write to...

Page 219: ...re frequency change with a voltage change The MPMU sets the VCC_APPS and VCC_SRAM voltage and the core frequency to the values selected 5 Initiate a voltage change sequence and power mode concurrently by writing the power mode bits in the core PWRMODE register CP14 Register 7 6 The PWR_I2C and PMUs change the voltage enter the power mode exit the power mode according to its normal exit mechanism a...

Page 220: ...when a high temperature frequency change is initiated but voltage change sequences will not be initiated when software controlled frequency changes are initiated resulting in incorrect voltage settings Incorrect voltage settings can cause unpredictable behavior 8 8 3 4 11 High Temperature Frequency and Voltage Change When TVE is set to 1 a VCC_APPS and VCC_SRAM voltage change sequence may be initi...

Page 221: ...ence should be used to perform S W PI2C register accesses S W must make sure that the following code is executed in a single thread mode and that all interrupts except critical ones like Batt Fault detected are disabled before the following sequence is started This is to prevent another piece of S W from causing a PMIC event like LPM entry Read the PMER register and verify that the value read is 0...

Page 222: ... not affect the PMCR bits This is a read write register Ignore reads from reserved bits Write 0b0 to reserved bits Table 8 6 PMCR Bit Definitions Sheet 1 of 2 Physical Address 0x40F5_0000 PMCR Services Unit Power Management Unit User Settings Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SWGR reserved VIS VIE TIS TIE reserved reserved reserved reserved r...

Page 223: ... temperature condition with TIE set 10 R W TIE Interrupt Enable for Application Core Frequency Change Due to Temperature Condition 0 Do not send interrupt to the application core when the application core frequency is changed due to a temperature condition 1 Send an interrupt to the application core when the application core frequency is changed due to a temperature condition 9 2 reserved 1 R Writ...

Page 224: ...s SS3S is set when S3 mode is entered as a result of setting the S3 mode configuration in the application core PWRMODE register CP14 Register 7 Note Software S2 status SS2S is set when S2 mode is entered as a result of setting the S2 mode configuration in the application core PWRMODE register CP14 Register 7 Temperature sensor status TSS indicates the current temperature range of operation Part ty...

Page 225: ...or to entering low power states See Table 8 8 for details This is a read write register Ignore reads from reserved bits Write 0b0 to reserved bits 2 R Write 1 to Clear BFS Battery Fault Status 0 nBATT_FAULT has not been asserted since it was last cleared by a reset or by software 1 nBATT_FAULT has been asserted and caused the MPMU to enter S3 mode 1 R Write 1 to Clear SS3S Software S3 Status 0 The...

Page 226: ...o the continuation of the S3 and S2 exit sequence Low power supply ramp delay LPM_DEL Adjusts the power up time in 32 kHz timekeeping oscillator cycles from the completion of I2C commands used to enable the low voltage power supplies to the continuation of the D1 D2 and D3 exit sequences and when executing a Boerne frequency change S3 mode L0 converter enable L0_EN Selects between the low power re...

Page 227: ..._DEL System Power Supply Ramp Delay Sets the number of timekeeping oscillator 32 kHz cycles between assertion of SYS_EN system power supplies enabled and continuation of the power up sequence to 2n reset value 0b1100 for 125 ms delay 0b0000 0b1100 n SYS_DEL 0b1101 0b1111 n 12 Example For SYS_DEL 0b1100 0b1100 12 n 2n 212 4096 System Power Supply Ramp Delay 4096 x 1 32 768 kHz 125 ms 27 24 R W PWR_...

Page 228: ...WR_DEL if all the corresponding power supplies are detected to have powered up 1 Shorten the wake up delay SYS_DEL or PWR_DEL if all the corresponding power supplies are detected to have powered up 7 3 reserved 2 R W PUDH Pull up Pull down Disable 1 Pull up and pull downs in nGPIO_RESET EXT_WAKEUP 1 0 PWR_SCL and PWR_SDA are disabled 0 Pull up and pull downs in nGPIO_RESET EXT_WAKEUP 1 0 PWR_SCL a...

Page 229: ...the PXA300 Processor and PXA310 Processor Electrical Mechanical and Thermal Specification for this time duration If a falling edge is to be detected on a signal the signal must be held high for a minimum time then low for a minimum time Refer to the PXA300 Processor and PXA310 Processor Electrical Mechanical and Thermal Specification for this time duration When nBATT_FAULT is asserted PWER assumes...

Page 230: ...er PECR PECR defined in Table 8 12 PECR indicates the current state of the EXT_WAKEUP pins and controls the interrupt generation for EXT_WAKEUP based interrupts The interrupt status bits are cleared by writing a 0b1 to them Writing a 0b0 to any of the interrupt status bits has no effect PECR status bits are maintained throughout operation and are independent of power states Note A write to the PEC...

Page 231: ...ite 0b0 to reserved bits Table 8 12 PECR Bit Definitions Physical Address 0x40F5_0018 PECR Services Unit Power Management Unit User Settings Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E1IS E1IE E0IS E0IE reserved IN1 IN0 Reset 0 0 0 0 0 0 Bits Access Name Description 31 R Write 1 to Clear E1IS EXT_WAKEUP 1 Interrupt Status 0 Interrupt was not due to E...

Page 232: ... PCMR BIE 1 or will enter S3 mode if PCMR BIE 0 When the battery fault event is masked PMER BFME is set to 1 if PCMR BIE 0 and the nBATT_FAULT signal is asserted the MPMU will enter S3 mode as expected PMER BFME has no effect on S3 entery when PCMR BIE 0 When the battery fault event is masked PMER BFME is set to 1 if PCMR BIE 1 and the nBATT_FAULT signal is asserted the MPMU will take no action du...

Page 233: ...uency changesS W accesses to the PI2C registers The user must write 0x0f to the PMER and verify the write has completed before writing to either the PWRMODE or CLKCFG registers attempting any access to PI2C registers in the application core Writing to the PMER prior to writing the PWRMODE and CLKCFG registers accessing PI2C registers will enable the EXT_WAKEUP 1 0 and RTC events so they will be de...

Page 234: ...requency change a processor system clocks change or an application subsystem D0 D1 D2 or S2 power mode change The FVE bit sends hardware controlled PWR_I2C commands to execute the voltage change Power change enable PVE Enables the PWR_I2 C to transmit commands to enable or disable the VCC_APPS and VCC_SRAM power supply when the application subsystem is entering D3 or when the MPMU is entering S2 o...

Page 235: ...er is not initiated to change power supply voltage levels during a processor system frequency change or power mode changes 1 The voltage change sequencer is initiated during a processor system frequency change or when the subsystem is entering or exiting low power states that require voltage level changes 30 R W PVE Power Change Enable 0 The voltage change sequencer is not initiated to enable disa...

Page 236: ...fication Proprietary Information December 13 2006 Not approved by Document Control For review only 8 10 Register Summary Table 8 15 shows the registers associated with the power management unit and the physical addresses used to access them Table 8 15 Power Management Unit Register Summary Address Name Description Page 0x40F5_0000 PMCR Power Management Unit Control register 222 0x40F5_0004 PSR Pow...

Page 237: ...Unit 9 9 1 Overview See the Overview in Chapter 9 Services Clock Control Unit in Vol I System and Timer Configuration Developers Manual The slave PMU BPMU is responsible for the power management and reset functions of the application subsystem including power management of the Intel XScale microarchitecture core and its internal SRAM Power states controlled by the BPMU are referred to as D states ...

Page 238: ...gure 9 1 Application Subsystem Power States Table 9 1 Summary of Application Subsystem Dx States Module Power States BPMU States D0 All subsystem power domains are powered on D1 BPMU some of the SRAM arrays and the mini LCD are powered on but the core and all other peripherals are in state retaining mode D2 BPMU is powered on core SRAM arrays and all peripherals including the mini LCD are in state...

Page 239: ...t unit contains the follow sections Reset management Power management Voltage management 9 2 1 Reset Management The application subsystem can be reset by one of four reset sources from the services unit MPMU The MPMU is the originator of resets and the BPMU is the coordinator of the resets in the application subsystem The Application Subsystem Reset Status Register ARSR records the kind of reset t...

Page 240: ...ons When system reset is entered the only activity inside the subsystems is the stabilization of the timekeeping oscillator The remaining internal clocks are stopped and the chip is fully static Normal boot up sequencing begins with all units in the application subsystem starting with their predefined reset conditions Core software must examine the Application Subsystem Reset Status Register ARSR ...

Page 241: ... must examine the Application Subsystem Reset Status Register ARSR to determine if the reset source was a GPIO reset 9 2 1 3 Low Power State Exit Reset Low power state exit reset is invoked when the BPMU exits D4 power state In low power state exit reset all units in the application subsystem that were powered off are reset to their predefined reset states Low power state exit reset is controlled ...

Page 242: ...an be changed See Section 9 2 2 1 2 D1 State for more information D2 state The core and most of the peripheral modules and internal SRAM arrays can be placed in a low power state where state is retained but no activity is allowed All clock sources except to the BPMU clocks OS timers mini LCD and mini SRAM controller are disabled and the external low voltage power supplies VCC_APPS and VCC_SRAM can...

Page 243: ...re driven entry sequence If nBATT_FAULT is asserted and the BIE bit is cleared to 0 the MPMU automatically transitions to S3 with the application subsystem entering D4 state with the result being the complete loss of state information in the application subsystem In this case no interrupt is sent to the core 9 2 2 1 2 D1 State D1 state offers lower power consumption by placing the core and most of...

Page 244: ... unable to recover from D1 state Entering D1 State from D0 State Entry into D1 state from D0 state is performed by writing the mode bits in the Core PWRMODE Register CP14 Register 7 to D1 state The SW should make sure LCD controller completes displaying the current frame buffer The sequence for entering D1 state is the following All processor activity is stopped and all interrupt requests to the p...

Page 245: ...ior in D1 State In D1 state all application subsystem clocks are derived from the ring oscillator clock The PD_BPMU and selected PD_ARx units are operational The BPMU OS timers mini LCD and the mini SRAM are all operational All other application subsystem modules including the core are in the low power state retaining mode Any SRAM bank that is not in the low power state retaining mode can be acce...

Page 246: ...state The ring oscillator is used as a temporary clock source for the core and application subsystem peripherals if PCCE bit in Application Subsystem Clock Configuration Register ACCR is set to 1 Unless specifically disabled the core PLL is enabled and reprogrammed with the corresponding values in the Application Subsystem Clock Configuration Register ACCR Unless specifically disabled the system P...

Page 247: ...ubsystem D2 Configuration Register AD2R must be set for the application subsystem SRAM banks that are to retain state during D2 state The PD_BPER power domains always retain state in D2 state The PD_BPMU power domain always remains powered up in D2 state The memory controller must be configured properly to ensure DDR SDRAM contents are maintained during D2 state See the Memory Controller chapter f...

Page 248: ...PMU initiates voltage change sequence for VCC_APPS and VCC_SRAM for D2 state D2 state wake ups enabled in Application Subsystem Wake Up from D2 to D1 State Enable Register AD2D1ER and Application Subsystem Wake Up from D2 to D0 State Enable Register AD2D0ER and activated BPMU notifies the MPMU of D2 entry The MPMU completes actions for D2 entry by disabling the core PLL disabling the ring oscillat...

Page 249: ...rtion of a D2 to D0 state wake up event If needed BPMU initiates voltage change sequence for VCC_APPS and VCC_SRAM for D0 state Power is restored and reset asserted to any SRAM arrays with D2 state unit operational bits cleared Refer to PCFR register in services unit for information about power ramp up The units selected by the D2 state unit operation bits and PD_BPER exit a low power state The ri...

Page 250: ...e application subsystem except for the units programmed to retain their state in the AD3R Bit Definitions the BPMU and OS timer Because internal activity has stopped recovery from D3 state must be through an external wake up event OS timer event or a RTC event Because all state has been lost in the application subsystem the state of the core is reset and recovery begins from the core reset vector ...

Page 251: ...subsystem MFPs are set for D3 state operation The BPMU asserts a reset for all application subsystem peripheral logic powered by VCC_APPS and all units not selected by the D3 state unit operation bits see Section 9 3 11 Application Subsystem D3 Configuration Register AD3R for more information on these bits The BPMU OS timer and units selected by the D3 state unit operation bits are not reset The u...

Page 252: ...er AD3ER are designed to bring the processor from D3 to D0 application subsystem state Wake ups controlled by the PWER register in the MPMU are designed to transfer the MPMU from S2 to S0 This implies that if the part is in S2 D3 then both AD3ER and PWER registers need to have a wake up enabled to return to S0 D0 Assertion of nBATT_FAULT while BIE bit is set to 1 results in exiting to D0 state to ...

Page 253: ...ing down all units in the application subsystem including the BPMU clocks OS timers mini LCD and mini SRAM controller The penalty for this low power state is that all state is lost and there is no activity inside the application subsystem Because internal activity has stopped recovery from D4 state must be through an external wake up event or a RTC event detected by the MPMU Because all state has ...

Page 254: ...e set for D4 state operation The BPMU asserts a reset for all application subsystem peripheral logic including the SRAM arrays and the OS timer The BPMU notifies the MPMU of D4 entry The MPMU completes actions for S3 entry by Asserting reset to the BPMU Disabling the core PLL Disabling the ring oscillator if enabled Disabling the system PLL Disabling the processor oscillator Deasserting PWR_EN and...

Page 255: ...es The MPMU waits the number of timekeeping oscillator cycles specified by the PWR_DEL bits in the Power Management Unit General Configuration register PCFR if PCFR SWDD is clear before continuing the wake up sequence If PCFR SWDD is set the MPMU exits the PWR_DEL delay count when VCC_APPS and VCC_SRAM voltages are detected and continues the wake up sequence The MPMU enables the processor 13 MHz o...

Page 256: ...uring the transition into the low power state the BPMU completes the transition and upon reaching the target power state immediately begins a new transition back to the run mode Due to synchronization across clock domains and other overhead there is a finite time interval between the software write to Core PWRMODE Register CP14 Register 7 to initiate a low power state and the BPMU wake detection w...

Page 257: ...ct_Status MTS_S Displays the current setting of the MTS value NOTE Any write to the MTS value must be followed by a polling of this field until the two match D1 state status D1S is set when D1 state is entered D2 state status D2S is set when D2 state is entered D3 state status D3S is set when D3 state is entered The status flags are cleared by writing 0b1 to them Writing 0b0 has no effect System a...

Page 258: ...t to support XN 2 0b011 0b111 Reserved Note SW needs to frequency change after writing updating this register 11 reserved 10 8 R W MTS_S Maximum Turbo Setting_Status 0b000 Reserved 0b001 VCC_APPS voltage has been set to support XN 1 0b010 VCC_APPS voltage has been set to support XN 2 0b011 0b111 Reserved Note SW needs to frequency change after writing updating this register 7 3 reserved 2 R Write ...

Page 259: ...and Control in Vol I System and Timer Configuration Developers Manual This is a read write register Ignore reads from reserved bits Write 0b0 to reserved bits Table 9 4 ARSR Bit Definitions Physical Address 40F4_0004 ARSR Slave Power Management Unit User Settings Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved GPR LPMR WDT HWR Reset 0 0 0 1 Bits A...

Page 260: ...m D3 to D0 State 0 Disable wake up due to timer event 1 Enable wake up due to timer event 29 R W WETSI Wake Up Options for Touch Screen Interface from D3 to D0 State 0 Disable wake up due to TSI event 1 Enable wake up due to TSI event Note This value needs to be programmed same value as AD1D0ER 29 28 R W WEUSBH Wake Up Options for USB Host Port from D3 to D0 State 0 Disable wake up due to USB Host...

Page 261: ...e 0b0 to reserved bits 20 R W WEUSIM1 Wake Up Options for USIM Port 1 from D3 to D0 State 0 Disable wake up due to USIM port 1event 1 Enable wake up due to USIM port 1 event 19 R W WEUSIM0 Wake Up Options for USIM Port 0 from D3 to D0 State 0 Disable wake up due to USIM port 0 event 1 Enable wake up due to USIM port 0 event 18 17 reserved 16 R W WE_OTG Wake Up Options for USBOTG Input 0 Disable wa...

Page 262: ...d WS_OTG WS_GENERIC 13 0 Reserved WS_EXTERNAL Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Access Name Description 31 R Write 1 to clear WSRTC Wake Up Status for RTC from D3 to D0 State 0 No wake up occurred due to RTC alarm 1 Wake up occurred due to RTC alarm 30 R Write 1 to clear WSOST Wake Up Status for OS Timer from D3 to D0 State 0 No wake up occurred due to timer event 1 ...

Page 263: ...due to USIM port 1event 1 Wake up occurred due to USIM port 1 event 19 R Write 1 to clear WSUSIM0 Wake Up Status for USIM Port 0 from D3 to D0 State 0 No wake up occurred due to USIM port 0 event 1 Wake up occurred due to USIM port 0 event 18 17 reserved 16 R Write 1 to clear WSOTG Wake Up Status for a Rising Edge from USB USBOTG Port from D3 to D0 State 0 No wake up occurred due to USBOTG port 1 ...

Page 264: ... reads from reserved bits Write 0b0 to reserved bits Table 9 7 AD2D0ER Bit Definitions Sheet 1 of 3 Physical Address 40F4_0010 AD2D0ER Slave Power Management Unit User Settings Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WERTC WEOST WETSI WEUSBH reserved WEUSB2 reserved WEMSL0 WEMUX3 WEMUX2 WEKP WEUSIM1 WEUSIM0 reserved WE_OTG WE_GENERIC 13 0 WE_EXTERN...

Page 265: ... a rising edge from USB EDMUX2 port from D2 to D0 state EDMUX2 port is the GPIO pads with alternate funtion usb_p3_1 usb_p3_3 usb_p3_5 0 Disable wake up due to EDMUX2 port 1 Enable wake up due to EDMUX2 port 21 R W WEKP Wake up options for a keypad from D2 to D0 state 0 Disable wake up due to an edge detect on a keypad IO 1 Enable wake up due to an edge detect on a keypad IO 20 R W WEUSIM1 Wake up...

Page 266: ...se bits are cleared by writing 0b1 to them Writing 0b0 to any status bit has no effect This is a read write register Ignore reads from reserved bits Write 0b0 to reserved bits 15 2 R W WE_GENERIC n Wake up options for generic event inputs from D2 to D0 state where n 0 13 0 Disable wake up due to generic event n edge detect 1 Enable wake up due to generic event n edge detect 1 0 R W WE_EXTERN AL Wa...

Page 267: ...ed WS_EXTERNAL Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Access Name Description 31 R Write 1 to clear WSRTC Wake up Status for RTC from D2 to D0 state 0 No wake up occurred due to RTC alarm 1 Wake up occurred due to RTC alarm 30 R Write 1 to clear WSOST Wake up Status for OS Timer from D2 to D0 state 0 No wake up occurred due to timer event 1 Wake up occurred due to timer e...

Page 268: ... to D0 state 0 No wake up occurred due to USIM port 1event 1 Wake up occurred due to USIM port 1 event 19 R Write 1 to clear WSUSIM0 Wake up Status for USIM port 0 from D2 to D0 state 0 No wake up occurred due to USIM port 0 event 1 Wake up occurred due to USIM port 0 event 18 17 reserved 16 R Write 1 to clear WSOTG Wake up Status for USBOTG port from D2 to D0 state 0 No wake up occurred due to US...

Page 269: ...orresponding wake up sources cause an application subsystem wake up from D2 to D1 state Unlike the other Power Transition Enable registers the D2 to D1 transition can happen only as a result of real time clock alarm This is a read write register Ignore reads from reserved bits Write 0b0 to reserved bits 9 3 8 Application Subsystem Wake Up from D2 to D1 Status Register AD2D1SR AD2D1SR defined in Ta...

Page 270: ...t approved by Document Control For review only 9 3 9 Application Subsystem Wake Up from D1 to D0 State Enable Register AD1D0ER AD1D0ER defined in Table 9 11 selects whether or not the corresponding wake up sources cause an application subsystem wake up from the D1 to D0 state For details on programming a GPIO pin as a wake up source refer to Chapter 4 Pin Descriptions and Control in Vol I System a...

Page 271: ...UX3 WEMUX2 WEKP WEUSIM1 WEUSIM0 WEMLCD reserved WEOTG WE_GENERIC 13 0 Reserved WE_EXTERNAL Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Access Name Description 31 R W WERTC Wake up options for RTC from D1 to D0 state 0 Disable wake up due to RTC alarm 1 Enable wake up due to RTC alarm 30 R W WEOST Wake up options for OS Timer from D1 to D0 state 0 Disable wake up due to timer...

Page 272: ...ypad IO 20 R W WEUSIM1 Wake up options for USIM port 1 from D1 to D0 state 0 Disable wake up due to USIM port 1event 1 Enable wake up due to USIM port 1 event 19 R W WEUSIM0 Wake up options for USIM port 0 from D1 to D0 state 0 Disable wake up due to USIM port 0 event 1 Enable wake up due to USIM port 0 event 18 R W WEMLCD Wake up options for mini LCD from D1 to D0 state 0 Disable wake up due to m...

Page 273: ...application subsystem wake up from D1 to D0 state These bits are cleared by writing 0b1 to them Writing 0b0 to any status bit has no effect This is a read write register Ignore reads from reserved bits Write 0b0 to reserved bits 1 0 R W WE_EXTERN AL n Wake up options for external event inputs from D1 to D0 state where n 0 or 1 These are communicated via Services unit 0 Disable wake up due to exter...

Page 274: ...D reserved WSOTG WS_GENERIC 13 0 Reserved WS_EXTERNAL Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Access Name Description 31 R Write 1 to clear WSRTC Wake up Status for RTC from D1 to D0 state 0 No wake up occurred due to RTC alarm 1 Wake up occurred due to RTC alarm 30 R Write 1 to clear WSOST Wake up Status for OS Timer from D1 to D0 state 0 No wake up occurred due to time...

Page 275: ...port 1 from D1 to D0 state 0 No wake up occurred due to USIM port 1event 1 Wake up occurred due to USIM port 1 event 19 R Write 1 to clear WSUSIM0 Wake up Status for USIM port 0 from D1 to D0 state 0 No wake up occurred due to USIM port 0 event 1 Wake up occurred due to USIM port 0 event 18 R Write 1 to clear WSMLCD Wake up Status for mini LCD from D1 to D0 state 0 No wake up occurred due to mini ...

Page 276: ...ate unit operation bits select which internal SRAM arrays only associated non SRAM array logic is not powered used by the application subsystem retain their states when the application subsystem is in D3 all units except PMU are reset state operation bits in AD3R affects only memories used by the application subsystem 1 0 R Write 1 to clear WS_EXTERN AL n Wake up Status for external event inputs f...

Page 277: ...n state and operation when the application subsystem is in D2 state Disabled units registers take their reset values at D2 exit The core and all peripherals retain state in D2 state This is a read write register Ignore reads from reserved bits Write 0b0 to reserved bits Table 9 13 AD3R Bit Definitions Physical Address 40F4_0030 AD3R Slave Power Management Unit User Settings Bit 31 30 29 28 27 26 2...

Page 278: ...e application subsystem is in D1 state Disabled units are inaccessible in D1 state but retain state In D1 state the core retains state and both PLLs are turned off This is a read write register Ignore reads from reserved bits Write 0b0 to reserved bits 1 R W AD2_R1 D2 state retain state application subsystem internal SRAM lower bank array 1 0 Lower bank array 1 is off when BPMU is in D2 1 Lower ba...

Page 279: ...ts Write 0b0 to reserved bits 1 R W AD1_R1 D1 state retain state application subsystem internal SRAM lower bank array 1 0 Lower bank array 1 retains state in D1 state 1 Lower bank array 1 is entirely powered when BPMU is in D1 state 0 R W AD1_R0 D1 state retain state application subsystem internal SRAM lower bank array 0 0 Lower bank array 0 retains state in D1 state 1 Lower bank array 0 is entire...

Page 280: ...wer states Core C1 idle mode D1 LCD refresh state D2 standby state D3 sleep state S2 sleep state S3 deep sleep state D0CS or ring oscillator mode For details refer to the Slave Clock Control chapter Section 7 3 4 3 Ring Oscillator during D0 Mode The reset mode is D0 in which the core is fully active The instruction requires the following field assignments Opcode1 0 Opcode2 0 CRn 7 CRm 0 For detail...

Page 281: ...PWRMODE Bit Definitions Coprocessor 14 Register CR7 PWRMODE Slave Power Management Unit User Settings Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved reserved M Reset 0 0 0 0 Bits Access Name Description 31 3 reserved 2 0 W M Mode 0b000 S0 D0 C0 power state 0b001 S0 D0 C1 core Idle 0b010 S0 D1 C2 power state 0b011 S0 D2 C2 power state 0b100 Reserv...

Page 282: ...Marvell Page 282 Document Classification Proprietary Information December 13 2006 Not approved by Document Control For review only 0x40F4_0020 AD1D0ER Application Subsystem D1 to D0 State Wake Up Enable register 270 0x40F4_0024 AD1D0SR Application Subsystem D1 to D0 State Wake Up Status register 273 0x40F4_002C AGENP Application Subsystem General Purpose register 273 0x40F4_0030 AD3R Application S...

Page 283: ...o receive and transmit 1 Wire bus data and provides complete control of the 1 Wire bus through eight bit commands The processor loads commands reads and writes data and sets interrupt control through five registers All of the 1 Wire bus timing and control are generated within the 1 Wire bus master interface controller after the host loads a command or data When bus activity has generated a respons...

Page 284: ...s transferred from the transmit buffer and the process repeats Each of these registers has a flag that can be used as an interrupt source The transmit buffer empty flag W1INTR TBE is set when the transmit buffer is empty and ready to accept a new byte W1INTR TBE is cleared as soon as a byte is written into the transmit buffer The Tx Shift register empty flag W1INTR TEMT is set when the Tx Shift re...

Page 285: ...cept the presence pulse 10 3 3 1 Initialization Sequence Figure 10 2 shows the initialization sequence required to begin any communication with the bus slave See the PXA300 Processor and PXA310 Processor Electrical Mechanical and Thermal Specification for detailed timing information The 1 Wire bus master controller transmits a reset pulse The 1 Wire bus line is then pulled high by the external pul...

Page 286: ...0 3 Refer the PXA300 Processor and PXA310 Processor Electrical Mechanical and Thermal Specification for detailed timing information Figure 10 3 1 Wire Write Slots 10 3 3 3 Read Time Slots A read time slot is initiated when the 1 Wire bus master pulls the bus line low for the minimum required time and then releases it If the slave device is responding with a 0 the slave continues to hold the bus li...

Page 287: ...ffer two Interrupt status and enable registers and one Clock Divisor register The Command register is used to control the 1 Wire bus master interface controller functionality The Data register is a bidirectional register which is used for both transmission and reception of data from the 1 Wire bus The Interrupt registers hold the controller status and enable interrupts The Clock Divisor register m...

Page 288: ...is bit is unaffected by the state of the W1IER DQOE bit 2 W DQO ONE_WIRE output This bit is used to bypass 1 Wire bus master interface controller operations and drive the bus directly if needed 0 This bit is cleared on power up or reset Clearing this bit drives the bus high 1 Wire bus master interface controller operations only function while the 1 Wire bus is held high 1 Setting this bit drives t...

Page 289: ...ing connects the receive buffer to the data bus Table 10 3 shows the register bit definitions This is a read write register Ignore reads from reserved bits Write 0b0 to reserved bits 10 4 3 1 Wire Interrupt Register W1INTR This read only register contains flags from transmit receive and 1 Wire reset operations Only the presence detect flag PD is cleared when the W1INTR is read the other flags are ...

Page 290: ...l 0 This flag is cleared when the byte is read from the Receive Buffer register 1 This flag is set when there is a byte waiting to be read in the receive buffer 3 R TEMT Tx Shift register empty 0 This flag is cleared when data is shifted into the Trx Shift register from the transmit buffer 1 This flag is set after the last bit has been transmitted on the 1 Wire bus NOTE TEMT status bit is valid up...

Page 291: ...EPD Reset 0 0 0 0 1 0 Bits Access Name Description 31 8 Reserved Reserved 7 R W DQOE ONE_WIRE output enable This bit acts as a control select for the ONE_WIRE bus When set to 0 the bus is controlled by the 1 Wire bus master interface controller as normal 0 This bit defaults to 0 on power up or reset and should be left 0 unless users want to control the bus manually through the W1CMDR DQO bit 1 The...

Page 292: ...r 13 2006 Not approved by Document Control For review only 10 5 Register Summary Table 10 7 shows the 1 Wire bus master interface controller register allocations in the memory map Table 10 6 W1CDR Bit Definitions Physical Address 0x41B0_0010 W1CDR 1 Wire Interface User Settings Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DIVISOR Reset 0 0 0 0 ...

Page 293: ...vice generates a memory bus transaction The processor can access the peripheral bus through the bridge portion the DMA thus bypassing the system DMA Hence this document refers DMA as DMA Bridge The DMAC supports flowthrough transfers only Figure 11 1 provides an overview of the DMAC 11 2 Features The DMAC provides the following features Supports memory to memory peripheral to memory and memory to ...

Page 294: ... 294 Document Classification Proprietary Information December 13 2006 Not approved by Document Control For review only Supports flow control bits to process requests from peripheral devices Requests are not processed unless the flow control bit is set 11 3 Operation The DMAC can be configured to transfer data using flowthrough DMA The DMAC has 32 configurable channels See Figure 11 1 Figure 11 1 D...

Page 295: ...n whether a channel is active whether its target device is currently requesting service and the channel priority 11 3 1 1 DMA Channel Priority Scheme The DMA channel priority scheme helps to ensure that peripherals are serviced according to their bandwidth requirements Assign a higher priority to peripherals with higher bandwidth requirements and a lower priority to peripherals with lower bandwidt...

Page 296: ... STOPINTR is not cleared when the DSADRx DTADRx and DCMDx registers are programmed For a descriptor fetch transfer DCSRx STOPINTR is cleared when the DMA controller updates the DDADRx register Running For a descriptor fetch transfer after programming DDADRx and setting DCSRx RUN four words of descriptors are fetched from the memory and DCSRx STOPINTR continues to be clear For a no descriptor fetch...

Page 297: ...escriptor Mode Software Configuration DCSRx RUN DCSRx STOPINTR Resulting Channel State Descriptor Fetch mode Power up 0 1 Uninitialized Write to DDADRx before DCSRx RUN is set recommended flow 0 0 Valid descriptor not running Set DCSRx RUN after writing to DDADRx recommended flow 1 0 Running Set DCSRx RUN before writing to DDADRx not recommended 1 1 Invalid Write to DDADRx after DCSRx RUN is set n...

Page 298: ... for a request or starts the data transfer as determined by the DCMDx FLOW source and target bits After the channel transfers a number of bytes equal to the smaller of DCMDx SIZE and DCMDx LEN it either waits for the next request or continues with the data transfer until the DCMDx LEN reaches zero The channel stops or continues with a new descriptor fetch from the memory as determined by the DDADR...

Page 299: ... 2 1 1 Descriptor Branching If DDADRx BREN and DCSRx CMPST are set the DMAC fetches the next descriptor from the address in the DDADRx register 32 bytes If either of the bits is cleared DMAC fetches the next descriptor from the address in the DDADRx register DDADRx BREN is relevant only for descriptor fetch transfers DCSRx NODESCFETCH is cleared Figure 11 3 Descriptor Fetch Transfer Channel State ...

Page 300: ...t write a valid source physical address to the DSADRx register a target physical address to the DTADRx register and a command to the DCMDx register The DDADRx register is reserved in this mode and must not be written Next the DCSRx RUN bit must be set A descriptor fetch is not performed Depending on the DCMDx FLOWSRC and DCMDx FLOWTRG bits the channel either waits for a request or starts the data ...

Page 301: ...Detect normal channel stoppage by using the end interrupt DCSRx ENDINTR not the stop interrupt DCSRx STOPINTR See Table 11 15 for more information on the end interrupt If an error occurs during the fetch operation the channel enters the stopped state and remains there unless software clears the error condition and sets the DCSRx RUN bit field Note When a channel switches between a descriptor fetch...

Page 302: ...o 32 available channels If the on chip peripheral address resides in the DSADRx register the DCMDx FLOWSRC bit must be set to allow the processor to wait for the request before it initiates the transfer If the on chip peripheral address resides in the DTADRx register then the DCMDx FLOWTRG bit must be set If DCMDx ENDIRQEN is set a DMA interrupt is requested at the end of the last cycle associated...

Page 303: ...ocessor writes to the DCSRx RUN bit indicated by the channel that is configured to perform a memory to memory move The DCMDx FLOWSRC and DCMDx FLOWTRG bits must be cleared by software as soon as the descriptor is fetched The transfer then begins If DCMDx ENDIRQEN is set a DMA interrupt is requested at the end of the last cycle associated with the byte that caused DCMDx LEN to decrement to zero Not...

Page 304: ...twork transmit lists and network receiver buffer free lists Each demand for data that a peripheral generates is a memory data read or write A peripheral must not request a DMA transfer unless it is prepared to read or write the full data block 8 16 or 32 bytes and can handle trailing bytes that may occur at the end of a DMA transfer 11 3 4 2 Programmed I O Operations The processor can read and wri...

Page 305: ...DMAC encounters overhead while it works with misaligned data restricting memory addresses to 8 byte boundaries can be helpful Align the source and target addresses to 32 byte boundaries for optimal DMAC and memory controller performance By default during data transfers the DMA controller forces the least significant three bits of all external addresses to zeros and the least significant two bits o...

Page 306: ...not ended Note When a peripheral signals either an EOP or a TO from an external device the DMAC sets the end of receive EOR status bit in the corresponding channel Control Status register DCSRx See Table 11 15 for details End of descriptor chain EOC indicates that a DMA channel is at the end of its last descriptor After the current transfer DCMDx LEN 0 and DDADRx STOP 1 DMA signals the peripheral ...

Page 307: ... fetches the next descriptor 5 Since the peripheral still has trailing bytes in its RxFIFO it must make another request The peripheral must continue to issue such requests until the DMAC reads out all the trailing bytes and until an EOR is signaled 6 DCSRx EORINT set indicates that all trailing bytes were read and transferred to the required target The EORINT bit must be cleared before restarting ...

Page 308: ...emory address is byte aligned then the DALGN register must be programmed Refer to Section 11 4 9 for details If DCMDx INCSRCADDR or DCMDx INCTRGADDR is set then the DMAC increments the source or target address after each transaction by a number equal to the width of the peripheral bus peripheral For example if the DMAC is transferring 32 bytes of data from memory to a 4 byte wide peripheral bus pe...

Page 309: ...bytes of data from memory to the system bus peripheral in bursts of 32 bytes the DMAC increments the target address by 32 after the first burst and then by 16 after the second burst Table 11 5 Configuration for Memory to Memory Data Transfers Source Target Source Alignment bytes Target Alignment bytes DCMD INCSR CADDR binary DCMD INCTR GADDR binary DCMD WIDTH binary Memory Memory 1 1 1 1 00 Expans...

Page 310: ...ion chip in bursts of 32 bytes then the DMAC increments the target address by 32 after the first burst and then by 16 after the second burst Table 11 8 provides a quick reference for programming the DMAC for the on chip peripherals Table 11 7 Configuration for Companion Chip CC Related Data Transfers Source Target Source Alignment bytes Target Alignment bytes DCMD INCSR CADDR binary DCMD INCTR GAD...

Page 311: ...0_012C audio transmit 0x4050_0040 4 11 8 16 32 Target 0x4000_0130 surround transmit 0x4050_002C 4 11 8 16 32 Source 0x4000_117C Centre LFE transmit 0x4050_0038 4 11 8 16 32 Source 0x4000_ 1180 SSP1 receive 0x4100_0010 1 2 or 4 01 10 or 11 8 16 32 or trailing Source 0x4000_0134 transmit 0x4100_0010 1 2 or 4 01 10 or 11 8 16 32 or trailing Target 0x4000_0138 UART3 receive 0x4070_0000 1 or 4 01 or 11...

Page 312: ...r trailing Source or Target 0x4000_0174 endpoint F 0x4060_0318 4 11 8 16 32 or trailing Source or Target 0x4000_0178 endpoint G 0x4060_031C 4 11 8 16 32 or trailing Source or Target 0x4000_017C endpoint H 0x4060_0320 4 11 8 16 32 or trailing Source or Target 0x4000_0180 endpoint I 0x4060_0324 4 11 8 16 32 or trailing Source or Target 0x4000_0184 endpoint J 0x4060_0328 4 11 8 16 32 or trailing Sour...

Page 313: ...ing Target 0x4000_01D4 Receive 4 0x4140_0010 4 11 8 16 32 or trailing Source 0x4000_01D8 Transmit 4 0x4140_0010 4 11 8 16 32 or trailing Target 0x4000_01D C Receive 5 0x4140_0014 4 11 8 16 32 or trailing Source 0x4000_01E0 Transmit 5 0x4140_0014 4 11 8 16 32 or trailing Target 0x4000_01E4 Receive 6 0x4140_0018 4 11 8 16 32 or trailing Source 0x4000_01E8 Transmit 6 0x4140_0018 4 11 8 16 32 or trail...

Page 314: ...ly transfers LEN bytes of data associated with this descriptor build real descriptor desc 0 ddadr STOP desc 0 dsadr DSADR desc 0 dtadr DTADR desc 0 dcmd DCMD start the channel DMANEXT CHAN desc 0 DRUN 1 Example 11 1 Creating a Zero Length Descriptor The following example of code shows how to initialize a descriptor list for a channel that is running Allocate a new descriptor and make it an End Des...

Page 315: ...ices that require it In the following example the companion chip requires the DMA to read four descriptor words program a channel as indicated by descriptor and continue the transfer based on the new descriptor Such a companion chip makes the following requirements 1 When the companion chip asserts DREQ fetch four descriptor words from one of its ports 2 Based on the information contained in the d...

Page 316: ...ermine if the channel stopped in the last descriptor of the chain If it did manipulate the DDADRx register of this descriptor so that it points to the newly created end descriptor 7 Program the channel DDADRx register with the next descriptor created in Step 5 8 Set DCSRx RUN 1 Example 11 4 Using Software Implementation of Full and Empty Bits This example shows how to use the compare descriptor an...

Page 317: ... The following code is a chain of descriptors for full and empty bit implementation First Descriptor Set First Descriptor Compare and Branch Descriptor modes enabled No data transferred by this descriptor Source is indirectly addressed and target is directly addressed On a successful compare of FETBL0 with 0x0000 Descriptor chain branches to desc 1 4 32bits i e desc 2 If Compare fails then descrip...

Page 318: ... enabled No data transferred by this descriptor Source is indirectly addressed and target is directly addressed On a successful compare of FETBL1 with 0x0000 Descriptor chain branches to desc 5 4 32bits i e desc 6 If Compare fails then descriptor chain jumps to desc 5 Desc 5 stops the channel as Full and Empty bits were not both 0 desc 4 ddadr desc 5 BrEn 1 desc 4 dsadr FETBL1 desc 4 dtadr 0x0000 ...

Page 319: ...e 11 19 summarizes the register names addresses and descriptions 11 4 1 DMA Request to Channel Map Register DRCMRx These registers map the DMA request to a channel These are read write registers Ignore reads from reserved bits Write 0b0 to reserved bits Table 11 9 DRCMR0 63 DRCMR64 99 Bit Definitions Sheet 1 of 2 Physical Address 0x4000_0100 0x4000_01FC1 0x4000_1100 0x4000_118C1 DRCMR0 DRCMR63 DRC...

Page 320: ...d on power up The address must be aligned to a 128 bit 4 word boundary DDADRx must not contain the address of any other internal peripheral register or DMA register as this causes a bus error The DDADRx register is reserved if the channel is performing a no descriptor fetch transaction These are read write registers Ignore reads from reserved bits Write 0b0 to reserved bits 4 0 R W CHLNUM Channel ...

Page 321: ...ss can be aligned to a byte boundary see Section 11 4 9 Improper configuration of the Alignment register defaults the source address to an 8 byte boundary Other restrictions on byte boundary alignment can apply for special DMA operations see Section 11 3 4 4 These are read write registers Ignore reads from reserved bits Write 0b0 to reserved bits 3 2 Reserved Reserved 1 R W BREN Enable Descriptor ...

Page 322: ...figured the address can be aligned to a byte boundary see Section 11 4 9 Improper configuration of the Alignment register defaults the target address to an 8 byte boundary Other restrictions on byte boundary alignment can apply for special DMA operations see Section 11 3 4 4 These are read write registers Ignore reads from reserved bits Write 0b0 to reserved bits Table 11 11 DSADR0 31 Bit Definiti...

Page 323: ...e 11 12 DTADR0 31 Bit Definitions Physical Address 0x4000_02x8 0x4000_03x8 DTADR0 DTADR31 DMA Controller User Settings Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TRGADDR Reset Bits Access Name Description 31 3 R W TRGADDR Target address Target address of the on chip peripheral external peripheral companion chip or address of a memory location 2 R W TR...

Page 324: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Access Name Description 31 R W INCSRCADDR Source address increment If the source address is an internal peripheral FIFO address or external I O address the address is not incremented on each successive access In these cases DCMDx INCSRCADDR must be cleared 0 Do not increment source address 1 Increment source address 30 R W INCTRGADDR Target address increment...

Page 325: ... Reserved 23 R W ADDRMODE or Reserved Addressing mode This bit controls the addressing mode for descriptor comparison and is valid only in the descriptor compare mode DCMDx CMPEN 1 Reserved if DCMDx CMPEN 0 If DCMDx CMPEN is set the bits specify the addressing modes of the source address and target address fields If either field contains an address the DMAC fetches the data at that address and use...

Page 326: ...ments to zero 20 18 Reserved 17 16 R W SIZE Maximum burst size Maximum burst size of each data transfer 0b00 Reserved 0b01 8 bytes 0b10 16 bytes 0b11 32 bytes The size must be less than or equal to the serviced peripheral FIFO trigger threshold to properly handle the respective FIFO trailing bytes 15 14 R W WIDTH or Reserved Width of the on chip peripheral This bit is a reserved field for operatio...

Page 327: ...e length of transfer in bytes LEN 0 means zero bytes for descriptor fetch transactions LEN 0 is an invalid setting for no descriptor fetch transactions Programming LEN 0 in the descriptor fetch mode when DCMD CmpEn is clear normal data transfer mode causes the channel to immediately discard the descriptor after it is fetched from memory If the descriptor chain has more descriptors the channel fetc...

Page 328: ...o reserved bits 11 4 7 DMA Channel Control Status Registers DCSRx These read write registers Table 11 15 contains the control and status bits for the channels Ignore reads from reserved bits Write 0b0 to reserved bits Table 11 14 DRQSR0 Bit Definitions Physical Address 0x4000_00E0 DRQSR0 DMA Controller User Settings Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 ...

Page 329: ... channel If the RUN bit is cleared in the middle of the burst the burst is completed before the channel stops Setting RUN starts the stopped channel If the channel is in a descriptor fetch transfer and RUN is set before writing a valid descriptor address to register DDADRx no descriptor fetch occurs This bit is reset as soon as it is cleared and when the channel stops normally After the channel st...

Page 330: ... channel is in uninitialized or stopped state 28 R W EORIRQEN Setting the End of Receive interrupt enable This bit triggers an interrupt on an EOR condition Clearing this bit does not generate an EOR related interrupt 0 Interrupt not triggered even if DCSRx EORINT is set 1 Enable Interrupt if DCSRx EORINT is set 27 R W EORJMPEN Jump to the next descriptor on EOR This bit controls the descriptor fl...

Page 331: ... another receive request 1 DMAC stops the channel that received an EOR from the mapped peripheral 25 W SETCMPST Set descriptor compare status This bit partially controls DCSRx CMPST Setting this bit sets DCSRx CMPST Clearing SETCMPST has no effect on DCSRx CMPST Software can set DCSRx CMPST even if the descriptor is not configured in the compare mode DCMDx CMPEN 0 0 No effect on DCSRx CMPST 1 Set ...

Page 332: ...ul compare of the source and target fields An unsuccessful comparison clears CMPST Refer to the description of DCMDx ADDRMODE for the various addressing modes used for this comparison For details regarding the descriptor compare mode refer to DCMDx CMPEN in Table 11 13 The DMAC updates CMPST only in descriptor compare mode DCMDx CMPEN 1 CMPST can be set and cleared by setting DCSRx SETCMPST and DC...

Page 333: ...Rx EORJMPEN for the behavior of the DMAC during this condition Note The EORINT bit must be cleared before restarting a channel 8 R REQPEND Request pending This bit indicates a pending request for the DMA channel REQPEND is cleared for a channel if that channel has no pending request or the request has just been issued to the memory interface in case of a read or write from the external companion c...

Page 334: ...DINTR End interrupt This bit indicates that the current descriptor finished successfully and that DCMDx ENDIRQEN is set 0 No interrupt 1 Interrupt was caused due to successful completion of the current transaction and DCMDx LEN 0 1 Read Writ e 1 to clear STARTINTR Start interrupt This bit indicates that the current descriptor was loaded successfully and that DCMDx STARTIRQEN is set 0 No interrupt ...

Page 335: ...TRICTLY PROHIBITED DMA Controller Copyright 12 13 06 Marvell CONFIDENTIAL Doc No MV TBD 00 Rev A December 13 2006 Document Classification Proprietary Information Page 335 Not approved by Document Control For review only A9379 01 No No Yes No No Yes No Yes Yes Receive request Wait for receive request Channel stopped DCSRx stopintr set Interrupt triggered if DCSRx StopIrqEn 1 Note Fetching the NextD...

Page 336: ...that corresponds to DCSRx STOPINTR are cleared by writing 1 to the corresponding interrupt bit in the DCSRx register 11 4 9 DMA Alignment Register DALGN DALGN Table 11 17 activates byte alignment for source and target addresses Each bit in the register corresponds to a DMA channel By default during data transfers the DMAC forces the least significant three bits for all external addresses to zeros ...

Page 337: ...sponse and the split completion are retried If the PIO transaction is a write instruction to a peripheral address domain the DMA posts the write instruction The DMA bridge indicates to the system bus that the PIO write is complete and then release the system bus The actual write transaction is then sent across the peripheral bus using microcoded instructions If software requires that a write compl...

Page 338: ... bit when a PIO transaction is still pending might lead to unpredictable results and is therefore not recommended The PIO transactions are always completed in the order they were issued irrespective of DPCSR BRGSPLIT Note 3 DPCSR BRGSPLIT is set by default reset value DPCSR BRGBUSY is a status bit which when set indicates a pending PIO transaction across the peripheral bus Any further PIO transact...

Page 339: ...for channel 9 329 0x4000_0028 DCSR10 DMA Control Status register for channel 10 329 0x4000_002C DCSR11 DMA Control Status register for channel 11 329 0x4000_0030 DCSR12 DMA Control Status register for channel 12 329 0x4000_0034 DCSR13 DMA Control Status register for channel 13 329 0x4000_0038 DCSR14 DMA Control Status register for channel 14 329 0x4000_003C DCSR15 DMA Control Status register for c...

Page 340: ...ap register for AC97 modem receive request 319 0x4000_0128 DRCMR10 Request to Channel Map register for AC97 modem transmit request 319 0x4000_012C DRCMR11 Request to Channel Map register for AC97 audio receive request 319 0x4000_0130 DRCMR12 Request to Channel Map register for AC97 audio transmit request 319 0x4000_0134 DRCMR13 Request to Channel Map register for SSP1 receive request 319 0x4000_01...

Page 341: ...Channel Map register for USB endpoint U request 319 0x4000_01B4 DRCMR45 Request to Channel Map register for USB endpoint V request 319 0x4000_01B8 DRCMR46 Request to Channel Map register for USB endpoint W request 319 0x4000_01BC DRCMR47 Request to Channel Map register for USB endpoint X request 319 0x4000_01C0 DRCMR48 Request to Channel Map register for MSL receive request 1 319 0x4000_01C4 DRCMR...

Page 342: ...ress register channel 3 323 0x4000_023C DCMD3 DMA Command Address register channel 3 324 0x4000_0240 DDADR4 DMA Descriptor Address register channel 4 320 0x4000_0244 DSADR4 DMA Source Address register channel 4 322 0x4000_0248 DTADR4 DMA Target Address register channel 4 323 0x4000_024C DCMD4 DMA Command Address register channel 4 324 0x4000_0250 DDADR5 DMA Descriptor Address register channel 5 32...

Page 343: ...mmand Address register channel 12 324 0x4000_02D0 DDADR13 DMA Descriptor Address register channel 13 320 0x4000_02D4 DSADR13 DMA Source Address register channel 13 322 0x4000_02D8 DTADR13 DMA Target Address register channel 13 323 0x4000_02DC DCMD13 DMA Command Address register channel 13 324 0x4000_02E0 DDADR14 DMA Descriptor Address register channel 14 320 0x4000_02E4 DSADR14 DMA Source Address ...

Page 344: ...channel 21 323 0x4000_035C DCMD21 DMA Command Address register channel 21 324 0x4000_0360 DDADR22 DMA Descriptor Address register channel 22 320 0x4000_0364 DSADR22 DMA Source Address register channel 22 322 0x4000_0368 DTADR22 DMA Target Address register channel 22 323 0x4000_036C DCMD22 DMA Command Address register channel 22 324 0x4000_0370 DDADR23 DMA Descriptor Address register channel 23 320...

Page 345: ...20 0x4000_03E4 DSADR30 DMA Source Address register channel 30 322 0x4000_03E8 DTADR30 DMA Target Address register channel 30 323 0x4000_03EC DCMD30 DMA Command Address register channel 30 324 0x4000_03F0 DDADR31 DMA Descriptor Address register channel 31 320 0x4000_03F4 DSADR31 DMA Source Address register channel 31 322 0x4000_03F8 DTADR31 DMA Target Address register channel 31 323 0x4000_03FC DCM...

Page 346: ... V E L L C O N F I D E N T I A L U N D E R N D A 1 2 1 0 1 0 5 0 69rlq62d f714peg4 Memec Headquarters Unique Tech Insight Impact UNDER NDA 12101050 MARVELL CONFIDENTIAL UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED PXA300 Processor and PXA310 Processor Vol I System and Timer Configuration Developers Manual Doc No MV TBD 00 Rev A CONFIDENTIAL Copyright 12 13 06 Marvell Page 346 Document Clas...

Page 347: ...ces of interrupts The internal events that take place in a peripheral and cause an interrupt are called secondary sources of interrupts Multiple secondary sources are usually mapped to a single primary source For example the DMA controller is a primary source of interrupts to the interrupt controller with 32 possible secondary sources Each interrupt source is set to generate either an IRQ or an FI...

Page 348: ...el interrupt bit Second level interrupt status provides additional information about the interrupt and is used inside the interrupt service routine After it reads the first level registers software reads the registers in the device to determine the function that is causing the interrupt In general multiple second level interrupts are ORed to produce a first level interrupt bit Interrupts are enabl...

Page 349: ...l in this chapter 12 4 1 Accessing Interrupt Controller Registers Most of the interrupt controller registers can be accessed through coprocessor registers Accessing the interrupt controller registers through the coprocessor registers significantly reduces access times The coprocessor mapped registers must be accessed in supervisory mode only Attempts to access the coprocessor mapped interrupt copr...

Page 350: ...is enabled To read from the coprocessor register use an MRC instruction MRC P6 0 Rd CRn C0 0 Rd Arm register and CRn Coprocessor register Note All registers except IPR and ICCR are readable in coprocessor access mode To write the interrupt controller register use an MCR instruction LDR Rd 0xdesired_val Loading core register with desired value MCR P6 0 Rd CRn C0 0 write the Arm register to CP6 regi...

Page 351: ...al ID is assigned according to bit positions The Interrupt Pending registers IPRs are set using these values as the peripheral ID Table 12 2 Summary of Bit Positions for Primary Sources Sheet 1 of 2 Bit Position Source Module Bit Field Description Peripher al ID IP 55 Not used 55 IP 54 Not used 54 IP 53 Not used 53 IP 52 Clock Controller Processor CCU interrupts 52 IP 51 DMEM Interrupt Dynamic mem...

Page 352: ...26 IP 25 DMA Controller DMA Channel service request 25 IP 24 Synchronous Serial Port 1 SSP_1 service request 24 IP 23 Flash Card Interface MMC1 MMC SDIO Flash Card 1 status Error detection 23 IP 22 UART1 Transmit or receive error in UART1 22 IP 21 UART2 Transmit or receive error in UART2 21 IP 20 UART3 Transmit or receive error in UART3 20 IP 19 Not Used 19 IP 18 I2 C I2 C service request 18 IP 17...

Page 353: ... 12 4 for details Table 12 3 ICPR Bit Definitions Sheet 1 of 4 Physical Address 0x40D0_0010 Coprocessor Register CP6 CR4 ICPR Interrupt Controller User Settings Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTC_AL RTC_HZ OST_3 OST_2 OST_1 OST_0 DMAC SSP1 MMC 1 UART1 UART2 UART3 reserved I2C LCD SSP2 USIM1 AC97 SSP4 PML USBC GPIO_x GPIO_1 GPIO_0 OST_4_11 ...

Page 354: ... A transmit or receive error in UART2 has NOT occurred 1 A transmit or receive error in UART2 has occurred 20 R UART3 UART3 0 A transmit or receive error in UART3 has NOT occurred 1 A transmit or receive error in UART3 has occurred 19 reserved 18 R I2C I2C 0 I2C service request has NOT occurred 1 I2C service request has occurred 17 R LCD LCD 0 LCD controller has NOT requested service 1 LCD control...

Page 355: ...her than GPIO_0 or GPIO_1 has been detected 9 R GPIO_1 GPIO_1 0 GPIO 1 edge has NOT been detected 1 GPIO 1 edge has been detected 8 R GPIO_0 GPIO_0 0 GPIO 0 edge has NOT been detected 1 GPIO 0 edge has been detected 7 R OST_4_11 OS Timers 4 11 0 OS timer match 4 11 has NOT occurred 1 OS timer match 4 11 has occurred 6 R PWR_I2C Power I2C 0 I2C Power Unit interrupt has NOT occurred 1 I2C Power Unit...

Page 356: ...pt Controller User Settings Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved reserved reserved reserved BCCU DMEMC WAKEUP 1 WAKEUP 0 reserved SGP MPMU USB 2 NAND INF ONE WIRE reserved reserved MMC 2 reserved GRAPHICS USIM 2 reserved resreved reserved CONSUMER IR CIF reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Access Name Description 31 21...

Page 357: ...ONE WIRE 0 The One Wire controller has NOT requested service 1 The One Wire controller has requested service 11 reserved 10 reserved 9 R MMC 2 0 The MMC2 controller has NOT requested service 1 The MMC2 controller has requested service 8 reserved 7 R GRAPHICS 0 The graphics controller has NOT requested service 1 The graphics controller has requested service 6 R USIM 2 0 The USIM2 controller has NOT...

Page 358: ...errupt that is waiting to be served In general software reads status registers of the controller causing the interrupt for detailed information to determine how to service the interrupt Interrupt bits in the ICPR and ICPR2 are read only and represent the logical OR of the status bits for a given interrupt in the source unit After an interrupt has been serviced the handler clears the pending interr...

Page 359: ...DMA channel service request has occurred interrupt level 25 0 and either mask bit 25 1 or DIM bit 0 24 R SSP1 SSP 1 0 One of the requirements for setting the bit has not been met 1 SSP 1 service request has occurred interrupt level 24 0 and either mask bit 24 1 or DIM bit 0 23 R MMC1 MultiMediaCard 0 One of the requirements for setting the bit has not been met 1 Flash card status has changed or an...

Page 360: ...ccurred interrupt level 16 0 and either mask bit 16 1 or DIM bit 0 15 R USIM1 USIM1 0 One of the requirements for setting the bit has not been met 1 Smart card interface status error has occurred interrupt level 15 0 and either mask bit 15 1 or DIM bit 0 14 R AC97 AC97 0 One of the requirements for setting the bit has not been met 1 AC97 interrupt has occurred interrupt level 14 0 and either mask ...

Page 361: ...r DIM bit 0 7 R OST_4_11 OS Timer 4 11 0 One of the requirements for setting the bit has not been met 1 OS timer match 4 11 has occurred interrupt level 7 0 and either mask bit 7 1 or DIM bit 0 6 R PWR_I2C Power I2C 0 One of the requirements for setting the bit has not been met 1 I2C power unit interrupt has occurred interrupt level 6 0 and either mask bit 6 1 or DIM bit 0 5 reserved 4 R KEYPAD Ke...

Page 362: ... 0 and either mask bit 0 1 or DIM bit 0 Table 12 6 ICIP2 Bit Definitions Sheet 1 of 3 Physical Address 0x40D0_009C Coprocessor Register CP6 CR6 ICIP2 Interrupt Controller User Settings Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved reserved reserved reserved BCCU DMEMC WAKEUP 1 WAKEUP 0 reserved SGP MPMU USB 2 NAND INF ONE WIRE reserved reserved ...

Page 363: ...b0 and interrupt level 47 0b0 14 R USB 2 0 No interrupt notification 1 interrupt occurs and mask bit 0 0b1 OR DIM bit 0b0 and interrupt level 46 0b0 13 R NAND INF 0 No interrupt notification 1 interrupt occurs and mask bit 0 0b1 OR DIM bit 0b0 and interrupt level 45 0b0 12 R ONE WIRE 0 No interrupt notification 1 interrupt occurs and mask bit 0 0b1 OR DIM bit 0b0 and interrupt level 44 0b0 11 rese...

Page 364: ...Information December 13 2006 10 46 am Preliminary Not approved by Document Control For review only 4 reserved 2 R CONSUMER IR Consumer IR 0 No interrupt notification 1 Consumer IR interrupt occurs and mask bit 0 0b1 OR DIM bit 0b0 and interrupt level 34 0b0 1 R CIF Capture Interface 0 No interrupt notification 1 Capture interface interrupt occurs and mask bit 0 0b1 OR DIM bit 0b0 and interrupt lev...

Page 365: ...22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTC_AL RTC_HZ OST_3 OST_2 OST_1 OST_0 DMAC SSP1 MMC 1 UART1 UART2 UART3 reserved I2C LCD SSP2 USIM1 AC97 SSP4 PML USBC GPIO_x GPIO_1 GPIO_0 OST_4_11 PWR_I2C reserved KEYPAD USBH1 USBH2 MSL1 SSP3 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Access Name Description 31 R RTC_AL Real Time Clock Alarm 0 No interrupt no...

Page 366: ...r receive error has occurred in UART1 interrupt level 22 1 and either mask bit 22 1 or DIM bit 0 21 R UART2 UART2 0 No interrupt notification 1 A transmit or receive error has occurred in UART2 interrupt level 21 1 and either mask bit 21 1 or DIM bit 0 20 R UART3 UART3 0 No interrupt notification 1 A transmit or receive error in UART3 has occurred interrupt level 20 1 and either mask bit 20 1 or D...

Page 367: ... occurred interrupt level 13 1 and either mask bit 13 1 or DIM bit 0 12 R PML Performance Monitor Unit 0 No interrupt notification 1 PML interrupt has occurred interrupt level 12 1 and either mask bit 12 1 or DIM bit 0 11 R USBC USB Client 0 No interrupt notification 1 USB Client interrupt has occurred interrupt level 11 1 and either mask bit 11 1 or DIM bit 0 10 R GPIO_X GPIO x 0 No interrupt not...

Page 368: ...and either mask bit 6 1 or DIM bit 0 5 reserved 4 R KEYPAD Keypad 0 No interrupt notification 1 Keypad Controller interrupt has occurred interrupt level 4 1 and either mask bit 4 1 or DIM bit 0 3 R USBH1 USB Host 1 0 No interrupt notification 1 USB Host interrupt 1 OHCI has occurred interrupt level 3 1 and either mask bit 3 1 or DIM bit 0 2 R USBH2 USB Host 2 0 No interrupt notification 1 USB Host...

Page 369: ...ved reserved MMC 2 reserved GRAPHICS USIM 2 reserved resreved reserved CONSUMER IR CIF reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Access Name Description 31 21 reserved 20 R BCCU 0 No interrupt notification 1 interrupt occurs and mask bit 0 0b1 OR DIM bit 0b0 and interrupt level 52 0b1 19 R DMEMC 0 No interrupt notification 1 interrupt occurs and mask bit 0 0b1 OR DIM bit 0b0 and interrupt leve...

Page 370: ...he processor is in S0 D0 C1 state and the ICCR DIM bit is set If the processor is in S0 D0 C1 state and the ICCR DIM bit is cleared irrespective of the mask bits in the ICMR or ICMR2 register The ICMR and ICMR2 bits are initialized and reset to zero which indicates that all interrupts are masked at reset and that ICMR and ICMR2 must be configured by software 7 R GRAPHICS 0 No interrupt notificatio...

Page 371: ... 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTC_AL RTC_HZ OST_3 OST_2 OST_1 OST_0 DMAC SSP1 MMC 1 UART1 UART2 UART3 reserved I2C LCD SSP2 USIM1 AC97 SSP4 PML USBC GPIO_x GPIO_1 GPIO_0 OST_4_11 PWR_I2C reserved KEYPAD USBH1 USBH2 MSL1 SSP3 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Access Name Description 31 R W RTC_AL Real Time Clock Alarm 0 Masked 1 RTC eq...

Page 372: ... be masked 19 reserved 18 R W I2C I2C 0 Masked 1 I2C interrupt is not to be masked 17 R W LCD LCD Controller 0 Masked 1 LCD controller interrupt is not to be masked 16 R W SSP2 SSP 2 0 Masked 1 SSP 2 service request interrupt is not to be masked 15 R W USIM1 USIM 1 0 Masked 1 Smart card interface status error interrupt is not to be masked 14 R W AC97 AC97 0 Masked 1 AC97 interrupt is not to be mas...

Page 373: ...PIO_0 0 Masked 1 GPIO 0 edge detect interrupt is not to be masked 7 R W OST_4_11 OS Timer 4 11 0 Masked 1 OS timer match 4 11 interrupt is not to be masked 6 R W PWR_I2C Power Manager I2C 0 Masked 1 I2C power interrupt is not to be masked 5 reserved 4 R W KEYPAD Keypad Controller 0 Masked 1 Keypad controller interrupt is not to be masked 3 R W USBH1 USB Host 1 0 Masked 1 USB host 1 interrupt OHCI ...

Page 374: ...ons Sheet 1 of 2 Physical Address 0x40D0_00A0 Coprocessor Register CP6 CR7 ICMR2 Interrupt Controller User Settings Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved reserved reserved reserved BCCU DMEMC WAKEUP 1 WAKEUP 0 reserved SGP MPMU USB 2 NAND INF ONE WIRE reserved reserved MMC 2 reserved GRAPHICS USIM 2 reserved resreved reserved CONSUMER IR...

Page 375: ...LR2 bit field is decoded to select which CPU interrupt is asserted Table 12 11 and Table 12 12 show the location of all interrupt level bits in the ICLR and the ICLR2 The ICLR and the ICLR2 registers are initialized to all zeros at reset and software must configure them to reflect the correct value for normal operation 9 R W MMC 2 MMC 2 0 Masked 1 Interrupt is not to be masked 8 reserved 7 R W GRA...

Page 376: ...1 PWR_I2C reserved KEYPAD USBH1 USBH2 MSL1 SSP3 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Access Name Description 31 R W RTC_AL Real Time Clock Alarm 0 RTC equals Alarm register interrupt creates an IRQ 1 RTC equals Alarm register interrupt creates an FIQ 30 R W RTC_HZ One Hz Clock 0 One Hz clock TIC interrupt creates an IRQ 1 One Hz clock TIC interrupt creates an FIQ ...

Page 377: ...troller 0 LCD controller interrupt creates an IRQ 1 LCD controller interrupt creates an FIQ 16 R W SSP2 SSP 2 0 SSP 2 service request interrupt creates an IRQ 1 SSP 2 service request interrupt creates an FIQ 15 R W USIM1 USIM 1 0 Smart card interface status error interrupt creates an IRQ 1 Smart card interface status error interrupt creates an FIQ 14 R W AC97 AC97 0 AC97 interrupt creates an IRQ 1...

Page 378: ...interrupt creates an IRQ 1 GPIO 0 edge detect interrupt creates an FIQ 7 R W OST_4_11 OS Timer 4 11 0 OS timer match 4 11 interrupt creates an IRQ 1 OS timer match 4 11 interrupt creates an FIQ 6 R W PWR_I2C Power I2C 0 I2C power unit interrupt creates an IRQ 1 I2C power unit interrupt creates an FIQ 5 reserved 4 R W KEYPAD Keypad 0 Keypad controller interrupt creates an IRQ 1 Keypad controller in...

Page 379: ...eserved reserved reserved reserved BCCU DMEMC WAKEUP 1 WAKEUP 0 reserved SGP MPMU USB 2 NAND INF ONE WIRE reserved reserved MMC 2 reserved GRAPHICS USIM 2 reserved resreved reserved CONSUMER IR CIF reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Access Name Description 31 21 reserved 20 R W BCCU Processor CCU 0 Service request interrupt creates an IRQ 1 Service request interrupt creates a FIQ 19 R W...

Page 380: ...le 12 13 shows the location of the DIM bit in the ICCR This is a read write register Ignore reads from reserved bits Reserved bits must be written with zeros 9 R W MMC 2 MMC 2 0 Service request interrupt creates an IRQ 1 Service request interrupt creates a FIQ 8 reserved 7 R W GRAPHICS Graphics 0 Service request interrupt creates an IRQ 1 Service request interrupt creates a FIQ 6 R W USIM 2 USIM 2...

Page 381: ...e changed during execution all interrupts must be masked The interrupts must be masked until the changes written to the IPRs have taken effect Interrupts can be disabled by writing to the Core Program Status register CPSR and altering its F bit and I bit The IPRx 31 is the valid bit 0b1 valid and 0b0 invalid The peripherals IDs range between 0 and 52 Peripheral IDs for different sources are shown ...

Page 382: ...ing peripheral for a particular interrupt level exists the corresponding peripheral ID field is invalidated The register is updated when an unmasked interrupt occurs If ICPs are partially defined the ICHP uses the partial information to determine the highest priority peripheral If none of the ICP fields are defined ICHP contains invalidated values in both fields After an interrupt is served and th...

Page 383: ...the registers Refer to Table 12 17 for the coprocessor address of the registers Table 12 15 ICHP Bit Definitions Physical Address 0x40D0_0018 Coprocessor Register CP6 CR5 ICHP Interrupt Controller User Settings Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VAL_IRQ reserved IRQ VAL_FIQ reserved FIQ Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Access Name Descri...

Page 384: ...C1 ICIP2 Interrupt Controller IRQ Pending register 2 358 0x40D0_00A01 ICMR2 Interrupt Controller Mask register 2 370 0x40D0_00A41 ICLR2 Interrupt Controller Level register 2 379 0x40D0_00A81 ICFP2 Interrupt Controller FIQ Pending register 2 365 0x40D0_00AC1 ICPR2 Interrupt Controller Pending register 2 353 0x40D0_0108 0x4 0DF_FFFF reserved 1 These registers are also mapped to coprocessors Refer to...

Page 385: ...he RTC controller 13 2 Differences Between the PXA300 Processor and PXA310 Processor There are no RTC differences between the PXA300 processor and the PXA310 processor 13 3 Features The PXA300 processor or PXA310 processor RTC controller has the following features Timer feature See Section 13 5 1 User programmable free running counter User programmable alarm register Resolution of one second Wrist...

Page 386: ...5 User programmable Trimmer register to generate a precise 1 Hz clock for the timer and wristwatch modules 13 4 Signal Description Table 13 1 describes the signal associated with the RTC controller 13 5 Operation The RTC controller uses the following modules to carry out its functionality Timer Wristwatch Stopwatch Periodic Interrupt Trimmer The peripheral bus interface block contains the RTC Stat...

Page 387: ...e The signals labeled 1 Hz clock in Figure 13 1 are internal timing signals and are not the same as the external signal HZ_CLK With the exception of the RTC Trim register all registers in the RTC controller are reset by both the hardware reset and the watchdog reset The RTC Trim register RTTR is reset by the hardware reset only The other resets low power mode exit reset and GPIO reset do not affec...

Page 388: ...s one counter register and one alarm register First the preferred alarm set conditions are written to the alarm register The corresponding alarm enable bit in the RTC Status register RTSR is then set If a counter has a count enable bit the corresponding count enable bit must be set to enable the counter to start counting The count enable bits for the corresponding counter registers reside in the R...

Page 389: ...gisters of the RTC controller and the module associated with each register Refer to Section 13 7 for the location of each of these registers 13 5 1 Timer Module The timer module of the RTC controller consists of a free running counter RTC Counter register RCNR that starts incrementing after the de assertion of a hardware reset or watchdog reset The count value is incremented at each rising edge of...

Page 390: ... RDAR2 and RYAR2 The wristwatch module runs in all power modes The counters sub module counts the current time and year The time of the day in terms of seconds minutes hours day of week and week of month is available through the RDCR The year month and day of month is available through the RYCR Alarm 1 has a corresponding alarm detect bit RTSR RDAL1 and a corresponding alarm enable bit RTSR RDALE1...

Page 391: ...sification Proprietary Information Page 391 Not approved by Document Control For review only Hour Day of week DOW Week of month WOM The RYCR counter refer to Table 13 14 the RYAR1 2 refer to Table 13 9 each have three fields Day of month DOM Month Year 13 5 2 2 Allowable Values for Wristwatch Register Fields For reference Table 13 3 provides all the valid and invalid values for each of the fields ...

Page 392: ... the count in February goes from 1 to 29 and the invalid data in this case is 30 31 and zero If the year is not a leap year the count in February goes from 1 to 28 therefore the invalid data in this case is 29 30 31 and zero 13 5 2 3 Effects of Data Written to Wristwatch Register Fields This section describes the effects of writing the wristwatch register fields with valid and invalid data The dis...

Page 393: ...re matched An exception in the use of the alarm registers is that if RYARx DOM contains valid data RDARx DOW and RDARx WOM are ignored for matching the data Example 13 1 Example Use of Alarm Registers When RYARx DOM Contains Valid Data In this example data is written RDAR1 SECONDS contains 0b00_0000 RDAR1 MINUTES contains 0b00_0000 RDAR1 HOURS contains 0b00_0000 RDAR1 DOW contains 0b111 RDAR1 WOM ...

Page 394: ...register1 SWAR1 and StopWatch Alarm register 2 SWAR2 The corresponding alarm detect bits and alarm enable bits are given in Table 13 2 The stopwatch 100th counter is clocked with a 100 Hz clock signal and increments at each rising edge of the 100 Hz clock signal The stopwatch seconds minutes and hours are clocked based on the trimmer 1 Hz clock Notice that because the 100th and seconds fields of t...

Page 395: ...e Whenever a new session is required the count enable bit must be set only after the new data is written into the alarm register The delay between the two writes must be at least two CPU clock cycles 13 5 4 Periodic Interrupt Module The periodic interrupt controller module of the RTC controller generates alarms periodically depending on the interval programmed into the Periodic Interrupt Alarm reg...

Page 396: ... the oscillator multiplexor must first be measured approximately 32 kHz using an accurate timebase such as a frequency counter Refer to Chapter 25 GPIO Multifunction Pins and Wake Up for details on the procedure to select the appropriate GPIO alternate function to make the oscillator multiplexor visible externally The trim is accomplished by dividing the output of the oscillator by an integer valu...

Page 397: ...actional trimming This trim exercise leaves an error of zero in trimming 13 5 5 2 2 Trim Example 2 Measured Value Has a Fractional Component A measured oscillator frequency with a fractional component occurs more frequently than an oscillator frequency without a fractional component Section 13 4 describes a measured oscillator frequency with a fractional component Example 13 4 Example of Measured ...

Page 398: ... Value With a Fractional Component To maintain an accuracy of 5 seconds per month the required accuracy is calculated to be Equation 13 4 Calculation to Maintain an Accuracy of 5 Seconds per Month The calculation in Equation 13 4 indicates that the 1 Hz clock output can be made very accurate through the use of the trim procedure Likewise use the trim procedure to compensate for a range of factors ...

Page 399: ...maximum of six 32 kHz clock cycles The RTC counter and alarm registers can be read at any time Reads reflect the value in the register after it increments or after it is written 13 6 1 RTC Trim Register RTTR RTTR defined in Table 13 5 configures the frequency of the 1 Hz clock The reset value of this register 0x0000_7FFF is such that a perfect 32 768 kHz crystal would result in a 1 Hz clock see Se...

Page 400: ... the corresponding alarm has occurred The alarm detect bits are set by the RTC controller logic if the corresponding enable bits are set and the alarm conditions have been met The alarm detect bits in this register are routed to the interrupt controller where they can be enabled to cause a second level interrupt The alarm detect bits are reset by writing 0b1 to the bit s to be cleared When the PXA...

Page 401: ...enabled 11 R W SWALE2 Stopwatch Alarm Enable for stopwatch alarm 2 0 Stopwatch alarm 2 is not enabled 1 Stopwatch alarm 2 is enabled 10 R WC SWAL2 Stopwatch Alarm 2 status 0 No stopwatch alarm 2 has been detected 1 Stopwatch alarm 2 has been detected SWAR2 matches SWCR and SWALE2 is set 9 R W SWALE1 Stopwatch Alarm Enable for stopwatch alarm 1 0 Stopwatch alarm 1 is not enabled 1 Stopwatch alarm 1...

Page 402: ...re equal and RTSR ALE is set then RTSR AL is set These are read write registers Ignore reads from reserved bits Write 0b0 to reserved bits 4 R WC RDAL1 Wristwatch Alarm 1 status 0 No wristwatch alarm 1 has been detected 1 Wristwatch alarm 1 has been detected RDAR1 matches RDCR and RYAR1 matches RYCR and RDALE1 bit is set 3 R W HZE HZ interrupt Enable 0 The HZ interrupt is not enabled 1 The HZ inte...

Page 403: ...ng wristwatch alarm detect bit RTSR RDAL1 2 Note Both the RDAR1 2 registers must be programmed in pairs If only one is used the other register must be programmed to a max value of 0xFFFF_FFFF to prevent any spurious wakeups Additionally user must first write to the RYARx registers as they will be locked once the corresponding RDARx registers are written These are read write registers Ignore reads ...

Page 404: ...troller logic sets the corresponding wristwatch alarm detect bit RTSR RDAL1 2 Note Both the RYAR1 2 registers must be programmed in pairs If only one is used the other register must be programmed to a max value of 0xFFFF_FFFF to prevent any spurious wakeups Additionally these registers should be written before writing to the RDARx registers as they are locked for protection once corresponding RDAR...

Page 405: ...ters must be programmed in pairs If only one is used the other register must be programmed to a max value of 0xFFFF_FFFF to prevent any spurious wakeups These are read write registers Ignore reads from reserved bits Write 0b0 to reserved bits 13 6 7 Periodic Interrupt Alarm Register PIAR PIAR defined in Table 13 11 is a 32 bit register Following each rising edge of the 1 kHz clock this register is...

Page 406: ...ock oscillator provides the 32 768 kHz clock These are read write registers Ignore reads from reserved bits Write 0b0 to reserved bits 13 6 9 RTC Day Counter Register RDCR RDCR defined in Table 13 13 reflects the current time in seconds minutes hours day of the week and week of the month The Week Of Month WOM and Day Of Week DOW fields are used together to represent the current day and week of the...

Page 407: ...s at 4095 This is a read write register Ignore reads from reserved bits Write 0b0 to reserved bits Table 13 13 RDCR Bit Definitions Physical Address 0x4090_0010 RDCR RTC Controller User Settings Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved WOM DOW HOURS MINUTES SECONDS Reset 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Access Name Descrip...

Page 408: ...ved bits Write 0b0 to reserved bits 13 6 12 Periodic Interrupt Counter Register RTCPICR RTCPICR defined in Table 13 16 contains the current count of the 1 kHz periodic interrupt counter and is clocked on the positive edge of the 1 kHz clock The RTCPICR increments only when the periodic interrupt count enable bit RTSR PICE is set If RTSR PICE is disabled the periodic interrupt counter stops increme...

Page 409: ...roller User Settings Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved MILLISECONDS Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Access Name Description 31 16 reserved 15 0 R W MILLISECONDS Periodic interrupt time in milliseconds Table 13 17 RTC Controller Register Summary Physical Address Name Description Page 0x4090_0000 RCNR RTC Counter register 40...

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Page 411: ...ets of timer channels The first set which provides one counter and four Match registers is clocked from a 3 25 MHz clock The other set which provides eight counters and eight Match registers can be clocked from the 32 768 kHz timer clock or a 13 MHz clock or an externally supplied clock providing a wide range of timer resolutions The latter set of timers can generate interrupts that can be used as...

Page 412: ...s block Throughout this section the terms compare and match are used to describe when a counter register OSCRx is being compared to an OS Match register OSMRx A compare occurs at the rising edge of every corresponding channel clock A match occurs when a compare is being performed and the value in OSCRx is the same as the value in OSMRx A match triggers an interrupt if the corresponding bit is set ...

Page 413: ...o this rule OMCRx C is cleared If OMCRx C see Table 14 2 is not set OSMR 7 4 are compared to OSCR4 to set the corresponding bit in OSSR M7 M4 and generate an interrupt if the corresponding interrupt enable bit in OIER is set Similarly OSMR8 11 are compared to OSCR8 to set OSSR M11 M8 and generate interrupts if the corresponding interrupt enable bits are set in OIER Watchdog reset When the watchdog...

Page 414: ...s interval and periodic timers synchronization features the ability to generate an output waveform and low power mode operability 14 4 5 Counter Resolutions The following sections discuss the possible resolutions for each Counter register in the OS timer 14 4 5 1 Clock Generation for Counter 0 Register The OSCR0 Counter register always uses the rising edge of the 3 25 MHz clock to increment This c...

Page 415: ... EXT_SYNC1 OMCR6 CRES is programmed to 0b001 the 32 768 KHz clock Figure 14 2 Example Reset of OSCR6 Based on Rising Edge of EXT_SYNC1 Channel 11 generates periodic output CHOUT1 Channel 10 generates periodic output CHOUT0 14 4 6 1 Output Generation for CHOUT 1 0 For channels 11 and 10 respectively if OMCRx P is set the channel counter OSCRx is periodic This periodic status means that when a match...

Page 416: ...y if snapshot mode is enabled for channel 9 a read from OSCR_9 results in copying the current value of OSCR_8 to OSNR This mode enables users to read the timer values in two channels simultaneously Snapshot mode is available only for Channels 11 and 9 14 4 8 Operation in Low Power Modes Counter operation for low power modes S0 D1 C2 S0 D2 C2 and S2 D3 C4 is summarized below Counter operation in D0...

Page 417: ...iodic control of the timer channels using OMCRx P and OMCRx R bits of channels 10 and 11 can respectively be used to drive CHOUT 1 0 The rest of timer channels work the same way as channel 10 and 11 except that they do not drive CHOUT 1 0 These are read write registers Ignore reads from reserved bits Write 0b0 to reserved bits Table 14 2 OMCR4 5 6 7 Bit Definitions Sheet 1 of 2 0x40A0_00C0 0x40A0_...

Page 418: ...ing this resolution continues operation in all power modes except S3 D4 C4 0b011 1 second This counter resolution is derived from the 32 768 KHz clock Any channel using this resolution continues operation in all power modes except S3 D4 C4 0b100 1 microsecond This counter resolution is derived from the 13 MHz clock Any channel using this resolution stops counting in S0 D2 C2 S2 D3 C4 or S3 D4 C4 m...

Page 419: ...3 2006 Document Classification Proprietary Information Page 419 Not approved by Document Control For review only 6 R W P Periodic Timer 0 The channel stops incrementing after detecting a match 1 The channel continues incrementing after detecting a match 5 4 R W S External Synchronization Control 0b00 No external synchronization 0b01 Reset OSCRx on the rising edge of EXT_SYNC0 0b10 Reset OSCRx on t...

Page 420: ...his resolution continues operation in all power modes except S3 D4 C4 0b0011 1 second This counter resolution is derived from the 32 768 KHz clock Any channel using this resolution continues operation in all power modes except S3 D4 C4 0b0100 1 microsecond This counter resolution is derived from the 13 MHz clock Any channel using this resolution stops counting in S0 D2 C2 S2 D3 C4 or S3 D4 C4 0b01...

Page 421: ...7 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved N CRES 3 C P S R CRES Reset 0 0 0 0 0 0 0 0 0 0 Bits Access Name Description 31 10 reserved 9 R W N Snapshot Mode Channel 9 0 Snapshot mode is disabled 1 Read from OSCR9 copies contents of OSCR8 to OSNR Channel 11 0 Snapshot mode is disabled 1 Read from OSCR11 copies contents of OSCR10 to OSNR 8 R W CRES 3 Used in co...

Page 422: ...dual ticks varies because the counter resolution is derived from the 32 768 KHz clock Any channel using this resolution continues operation in all power modes except S3 D4 C4 0b0011 1 second This counter resolution is derived from the 32 768 KHz clock Any channel using this resolution continues operation in all power modes except S3 D4 C4 0b0100 1 microsecond This counter resolution is derived fro...

Page 423: ...eset signal OSCR0 is compared to OSMR3 every rising edge of the 3 25 MHz clock When OWER WME is set and if a match is detected the output pin WDOG_RST is set and a reset is applied to the processor with most of internal states to be cleared Follow this procedure when using OSMR3 as a watchdog timer Each time the operating system services the register read the current value of the counter and add a...

Page 424: ... clear the corresponding interrupt status bit if that bit is already set See Table 14 7 This is a read write register Ignore reads from reserved bits Write 0b0 to reserved bits 14 5 5 OS Timer Count Register 0 OSCR0 This register is incremented on rising edges of the 3 25 MHz clock The counter can be read or written at any time This free running counter rolls over when the maximum value is reached...

Page 425: ...egister contains status bits to indicate whether a match has occurred between any of the 12 Match registers and the OS Counter registers These bits are set when a match event occurs and the corresponding interrupt enable bit is set in the OIER register If a non zero match value is loaded that equals the value of the corresponding OS Counter register or a Counter register is loaded with non zero a ...

Page 426: ...y Software must determine the interrupt source from the value in the OSSR register These are read write registers Ignore reads from reserved bits Write 0b0 to reserved bits 14 5 8 OS Timer Snapshot Register OSNR This register contains the snapshot value of either OSCR10 or OSCR8 When snapshot mode is enabled in OMCR9 and a read is performed from OSCR9 register the contents of OSCR8 are copied to O...

Page 427: ...S Timer Match 3 register 423 0x40A0_0010 OSCR0 OS Timer Counter register 0 425 0x40A0_0014 OSSR OS Timer Status register used for all counters 426 0x40A0_0018 OWER OS Timer Watchdog Enable register 424 0x40A0_001C OIER OS Timer Interrupt Enable register used for all counters 424 0x40A0_0020 OSNR OS Timer Snapshot register 426 0x40A0_0024 0x40A0_003C reserved 0x40A0_0040 OSCR4 OS Timer Counter regi...

Page 428: ...HIBITED PXA300 Processor and PXA310 Processor Vol I System and Timer Configuration Developers Manual Doc No MV TBD 00 Rev A CONFIDENTIAL Copyright 12 13 06 Marvell Page 428 Document Classification Proprietary Information December 13 2006 Not approved by Document Control For review only 0x40A0_00C8 OMCR6 OS Match Control register 6 417 0x40A0_00CC OMCR7 OS Match Control register 7 417 0x40A0_00D0 O...

Page 429: ...ovided using the core performance counters which allow additional functions to be monitored within the core These functions are connected to performance monitoring events numbered 0x80 0x87 of the third generation Intel XScale core in development 15 1 1 Differences Between the PXA300 Processor and PXA310 Processor There are no significant differences between the PXA300 processor or PXA310 processo...

Page 430: ...ithin the core to control the operation of the counters These registers are described in Chapter 10 Manzano Core External Architecture Specification EAS The EVTSEL register is used to select which of the eight processor level events are counted by each of the four counters Only eight events can be supplied to the core at a time of which only four can be monitored Note In general performance monito...

Page 431: ... Static memory queue occupied number of cycles when the static memory controller queue is not empty 19 Static memory queue occupied by more than one request number of cycles when the static memory controller queue has two or more requests 20 Static memory queue occupied by more than two requests number of cycles when the static memory controller queue has three or more requests 21 Static memory qu...

Page 432: ...cessor has spent in temperature range 3 49 Temperature level 4 time the processor has spent in temperature range 4 50 Core read write latency measurement Amount of time when core has more than one read write requests outstanding 51 Core read write latency measurement Amount of time when core has more than two read write requests outstanding 52 Core read write latency measurement Amount of time whe...

Page 433: ... System Bus 1 to dynamic static memory read write latency measurement Amount of time when System Bus 1 to dynamic static memory has more than four read write requests outstanding 62 System Bus 2 to internal memory read write latency measurement Amount of time when System Bus 2 to internal memory has more than one read write requests outstanding 63 System Bus 2 to internal memory read write latency...

Page 434: ...of different results to occur Again note that there are typically two events an abrupt stop event which causes an unrecoverable clock stop of the system unit and a debug event which places the system unit is a continuable debug state for example provokes a breakpoint routine to be run on the core these are regarded as separate occurrences Each result is separately programmed and more than one resu...

Page 435: ... One register is provided for each destination event All registers are identical even though some combinations may not provide useful function 15 5 2 1 MDU Intel XScale Breakpoint Register MDU_XSCALE_BP This register is used to cause the Intel XScale core to perform a breakpoint operation if triggered Refer to the Intel XScale core documentation for further information Table 15 2 PML_ESEL_ 7 0 Bit...

Page 436: ...etary Information December 13 2006 Not approved by Document Control For review only Table 15 3 MDU_XSCALE_BP Bit Definitions Physical Address 0x4600_FF40 MDU_XSCALE_BP PML MDU Module User Settings Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Reserved XCS EVENT XDB EVENT Reserved Reserved Reserved 2DG CS EVENT 2DG DB EVENT Reserved Reserved Rese...

Page 437: ... approved by Document Control For review only 15 5 2 2 MDU 2DG Stop Register MDU_2DG_EVENT Table 15 4 MDU_2DG_EVENT Bit Definitions Physical Address 0x4600_FF54 MDU_2DG_EVENT PML MDU Module User Settings Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Reserved XCS EVENT XDB EVENT Reserved Reserved Reserved 2DG CS EVENT 2DG DB EVENT Reserved Reserv...

Page 438: ... and multicore debug registers Table 15 5 MDU_CW_MATCH Bit Definitions Physical Address 0x4600_FF58 MDU_CW_MATCH PML MDU Module User Settings Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Reserved XCS EVENT XDB EVENT Reserved Reserved Reserved 2DG CS EVENT 2DG DB EVENT Reserved Reserved Reset 0 0 0 0 Bits Access Name Description 31 Reserved Rese...

Page 439: ...t Impact UNDER NDA 12101050 MARVELL CONFIDENTIAL UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED Performance Monitoring and Debug Copyright 12 13 06 Marvell CONFIDENTIAL Doc No MV TBD 00 Rev A December 13 2006 Document Classification Proprietary Information Page 439 Not approved by Document Control For review only 0x4600_FF50 Reserved 0x4600_FF54 MDU_2DG_EVENT MDU 2DG Stop register 437 0x4600...

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Page 441: ... buses are implemented as a multiplexer as opposed to a three state approach and the clients are allowed to request the bus without any limitations The System Bus 1 supports the System Bus 1 to switch connection the DMA controller the LCD controller the USB host controller the Intel Quick Capture Interface and the data flash interface The arbitration for bus access is performed by the arbiter whic...

Page 442: ...ced and decremented by one This continues until all counters have a value of zero Then the weighting values from ARB_CNTRL_x are reloaded into the counters and the process begins again For example if on System Bus 2 the USB 2 0 high speed controller is given a weight of six the switch core is given a weight of two and the 2 D graphics controller is given a weight of one the following would occur T...

Page 443: ... ARB_CNTRL_1 30 23 for System Bus 1 and ARB_CNTRL_2 31 29 26 for System Bus 2 Once the register is set the bus is granted to that client if no other client asks for the bus An exception to this rule occurs when overriding circumstances exist For instance if the LOCK_FLAG is set and the DMA is designated as the park client by setting ARB_CNTRL_1 DMA_PARK and a SWAP operation is in progress from the...

Page 444: ... Figure 16 1 All accesses to the memories from any of these masters flow through the switch to one of the memory controllers see Chapter 3 Memory Switch for more information The memory controllers all have internal buffers that work as a FIFO All requests to a particular memory are executed in order Programmers can program the system bus arbitration priorities enabling one of the masters on the bu...

Page 445: ...fined in Table 16 2 ARB_CNTRL_1 configures bus parking and the peripheral priority for the peripherals on System Bus 1 ARB_CNTRL_2 configures bus parking and the peripheral priority for the peripherals on System Bus 2 Writes to these register are immediately communicated to the arbiters Sensor LCD Panel DDR SDRAM IEEE 802 11 Cellular Baseband System Bus 1 System Bus 2 Peripheral Bus 1 Peripheral B...

Page 446: ...AG Reserved CAMERA_W T LCD_WT DMA_WT SWITCH_WT Reset 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 0 Bits Access Name Description 31 30 Reserved Reserved 29 R W DMA_SLV_PAR K DMA Slave Park 0 Bus is not parked with the DMA slave controller when idle 1 Bus is parked with the DMA slave controller when idle 28 R W SWITCH_SLV_ PARK System Bus 1 Switch Slave Park 0 Bus is not parked with the switch sla...

Page 447: ... bus can access the bus 21 16 Reserved Reserved 15 12 R W CAMERA_WT Camera Priority Value Values in this field determine the relative priority of camera requests for the bus vis a vis switch core LCD and DMA requests 11 8 R W LCD_WT LCD Priority Value Values in this field determine the relative priority of LCD requests for the bus vis a vis switch core Intel Quick Capture interface and DMA request...

Page 448: ... Park 0 Bus is not parked with the USB 2 0 client slave controller when idle 1 Bus is parked with the USB 2 0 client slave controller when idle 30 Reserved Reserved 29 R W SWITCH_SLV_ PARK System Bus 2 Switch Slave Park 0 Bus is not parked with the switch slave controller when idle 1 Bus is parked with the switch slave controller when idle 28 R W USB2_PARK USB 2 0 Client Master Park 0 Bus is not p...

Page 449: ...eview only 16 6 Register Summary Table 16 3 summarizes registers used for bus arbitration 3 0 R W SWITCH_WT Switch Core Priority Value Values in this field determine the relative priority of the switch core requests for the bus vis a vis USB 2 0 client and 2 D graphics requests Table 16 3 Internal System Bus Arbiter Register Summary Physical Address Name Description Page 0x4600_FE00 ARB_CNTRL_1 Sy...

Page 450: ...I D E N T I A L U N D E R N D A 1 2 1 0 1 0 5 0 69rlq62d f714peg4 Memec Headquarters Unique Tech Insight Impact UNDER NDA 12101050 MARVELL CONFIDENTIAL UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED PXA300 Processor and PXA310 Processor Vol I System and Timer Configuration Developers Manual Doc No MV TBD 00 Rev A CONFIDENTIAL Copyright 12 13 06 Marvell Page 450 Document Classification Propri...

Page 451: ...h other devices on the circuit board having a similar interface the integrity of the circuit board connections between devices JTAG also provides a mechanism for device debug via the Intel XScale CPU debug features JTAG logic includes a test access port TAP controller TAP pins an instruction register and test data registers TDRs These TDRs include the Boundary Scan register BSR the register used t...

Page 452: ...nstruction set Instruction register test data registers and data specific register 17 4 1 TAP Controller Reset The JTAG interface includes a TAP controller state machine To force the TAP controller into the correct state at powerup the nTRST pin can be asserted low or the TMS pin can be held high for five TCK cycles Marvell recommends that nTRST be driven from low to high either before or at the s...

Page 453: ...e connected between TDI and TDO and controlling the operation affecting that data These tasks are accomplished via a set of predefined instructions that can be either mandatory or optional as set forth in the IEEE Std 1149 1a 1993 user defined or private The IR is 11 bits wide 17 4 2 1 JTAG Instruction Set Three mandatory public instructions are supported extest sample preload and bypass Three opt...

Page 454: ...hout interfering with that normal operation The instruction causes BSR cells associated with output pins to sample the value being driven by or to the processor Similarly BSR cells associated with input pins sample the value being driven on the inputs When the TAP controller is in the Update DR state the preload instruction occurs on the falling edge of TCK This instruction causes the transfer of ...

Page 455: ...10 processor does not have the following pins USBH2_N USBH2_P USBH1_n and USBH1_P For any instructions that use the BSR the nBATT_FAULT and nRESET_IN pins must always be driven to a value of 0x1 because whenever either of these pins is in an active low state 0x0 the BSR logic powers down As such no JTAG instructions using the BSR can be performed with nBATT_FAULT or nRESET_IN at 0x0 or with the de...

Page 456: ...G instructions which are described the Intel XScale Core Developers Manual 17 4 4 TAP Controller The TAP controller is a 16 state synchronous state machine that controls the sequence of JTAG operations The TAP controller can be controlled via a bus master The TAP controller changes state only in response to a rising edge on TCK or powerup The value of the test mode state TMS input signal at a risi...

Page 457: ... state by asserting nTRST If the TAP controller exits the TLRS as a result of an erroneous low signal on the TMS line at the time of a rising edge on TCK for example a glitch due to external interference it returns to the test logic reset state following three rising edges of TCK with the TMS line at the intended high logic level Test logic operation is such that no disturbance is caused to on chi...

Page 458: ...is state the BSR retains it previous state The instruction does not change while the TAP controller is in this state If TMS is high on the rising edge of TCK the TAP controller enters the exit1 DR If TMS is low on the rising edge of TCK the TAP controller enters the shift DR state 17 4 4 5 Shift DR State In this state the test data register which is connected between TDI and TDO as a result of the...

Page 459: ...r is in this state all of the Test Data register shift register bit positions selected by the current instruction retain their previous values The instruction does not change while the TAP controller is in this state When the TAP controller is in this state and TMS is held high on the rising edge of TCK the TAP controller enters the select DR scan state If TMS is held low on the rising edge of TCK...

Page 460: ...state 17 4 4 14 Pause IR State The pause IR state allows the TAP controller to temporarily halt the shifting of data through the Instruction register The test data registers selected by the current instruction retain their previous values during this state The instruction does not change and the Instruction register retains its state The TAP controller remains in this state as long as TMS is held ...

Page 461: ...le 18 3 shows the summary memory map for region 0x8000_0000 to 0xFFFF_FFFF Accessing reserved portions of the memory map shown in Table 18 1 or Table 18 2 results in a data abort exception Accessing reserved portions of a particular peripheral s address space does not cause a data abort exception but the data returned is undefined The internal boot ROM is mapped to two different address spaces vir...

Page 462: ...00_0000 Reserved 64 MB 0x6C00_0000 Reserved 64 MB 0x6800_0000 Reserved 64 MB 0x6400_0000 Reserved 64 MB 0x6000_0000 Reserved 64 MB 0x5C00_0000 Internal SRAM 256 KB of 64 MB Internal Boot ROM 48K Note See Table 3 1 on page 3 5 0x5800_0000 System Bus 1 Internal Memory Memory Mapped registers Note 0x5400_0000 System Bus 2 Memory Mapped registers Note 0x5000_0000 System Bus 1 Camera Interface Memory M...

Page 463: ...USE STRICTLY PROHIBITED Memory Map Copyright 12 13 06 Marvell CONFIDENTIAL Doc No MV TBD 00 Rev A December 13 2006 Document Classification Proprietary Information Page 463 Not approved by Document Control For review only 0x0800_0000 Chip Select 0 256 MB 0x0400_0000 0x0000_0000 Table 18 2 Memory Map Part Two From 0x8000_0000 to 0xFFFF FFFF Sheet 1 of 2 Memory Map 0xFC00_0000 DDR SDRAM Chip Select 1...

Page 464: ...rol For review only 18 3 Memory Mapped Registers Summary Table 18 3 gives a summary of the memory map area from 0x4000_0000 to 0x5BFF_FFFF This area contains memory mapped registers stored within the various units and peripherals in the PXA300 processor or PXA310 processor 0xBC00_0000 DDR SDRAM Chip Select 0 1 GB Note MDCNFG DMAP must be set 0xB800_0000 0xB400_0000 0xB000_0000 0xAC00_0000 0xA800_0...

Page 465: ...000 GPIO Controller 0x40E0_0000 Slave Power Manager BPMU and Services Power Manager MPMU 0x40F0_0000 SSP1 0x4100_0000 MMC SD SDIO 1 0x4110_0000 Reserved 0x4120_0000 Services and Slave Clocks Controller 0x4130_0000 Reserved 0x4140_0000 KeyPad Interface 0x4150_0000 USIM 1 0x4160_0000 SSP2 0x4170_0000 Reserved 0x4180_0000 SSP3 0x4190_0000 SSP4 0x41A0_0000 1 Wire 0x41B0_0000 Reserved 0x41C0_0000 Consu...

Page 466: ...s exactly the same function appearing in both places This boot ROM is used to execute the initial start up code in all cases of reset and to provide various options for booting the device Additional information is provided in Chapter 2 Power On Reset and Boot Operation Performance Monitoring and Debug 0x4600_FF00 0x4600_FFFF Reserved 0x4601_0000 0x480F_FFFF Dynamic Memory Controller 0x4810_0000 Re...

Page 467: ... 5 0 6 9 r l q 6 2 d f 7 1 4 p e g 4 M e m e c H e a d q u a r t e r s U n i q u e T e c h I n s i g h t I m p a c t M A R V E L L C O N F I D E N T I A L U N D E R N D A 1 2 1 0 1 0 5 0 69rlq62d f714peg4 Memec Headquarters Unique Tech Insight Impact UNDER NDA 12101050 MARVELL CONFIDENTIAL UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED THIS PAGE INTENTIONALLY LEFT BLANK ...

Page 468: ... Ku Seoul 135 731 Korea Tel 82 0 2 551 6070 6079 Fax 82 0 2 551 6080 Radlan Computer Communications Ltd Atidim Technological Park Bldg 4 Tel Aviv 61131 Israel Tel 972 0 3 645 8555 Fax 972 0 3 645 8544 Worldwide Sales Offices Western US Marvell 700 First Avenue Sunnyvale CA 94089 USA Tel 1 408 222 2500 Fax 1 408 752 9028 Sales Fax 1 408 752 9029 Marvell 5400 Bayfront Plaza Santa Clara CA 95054 USA ...

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