DMN-8600 DVD Recorder System Processor
8-1
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
LSI Logic Confidential
Chapter 8
Host Slave Interface
This chapter describes the host slave interface and contains the following
sections:
•
Section 8.1, “Async Slave Interface with Host DMA”
•
Section 8.2, “Async Slave Interface Transfer Modes”
•
Section 8.3, “Async Slave WRITE and READ Protocols”
•
Section 8.4, “Host DMA Read/Write Protocol”
•
Section 8.5, “Power Management”
•
Section 8.6, “Host Interface Registers”
•
Section 8.7, “Host DMA Registers”
•
Section 8.8, “Master DMA Registers”
The Host processor port is configured differently for different processors.
It supports the following general features:
•
16- or 32-bit Host data bus
•
Host DMA target
•
WAIT and DTACK signalling for slow response time
•
Separate or combined Read and Write strobes
The DMN-8600 embedded host interface supports two modes:
•
Async Slave Interface with host DMA: An asynchronous,
demultiplexed address/data bus (See
) that provides local
DRAM and control register access to an external microcontroller
(Host) which may perform various control functions at the system
level.