LSI Logic Confidential
SIO Register Descriptions
15-23
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Bit 2 is for indicating when each programmed double
buffer (set in Addr_Ptr1/2, propagated to Addr_Ptr3/4)
has completed:
1 = Completed
On transmit: All data in programmed memory space has
drained out of the channel FIFO to the module;
On receive: Sufficient data to fill memory space has been
collected from the module.
R2T2
IR2 Transmit Interrupt 2 Status
22
R2T1
IR2 Transmit Interrupt 1 Status
21
R1R2
IR1 Receive Interrupt 2 Status
20
R1R1
IR1 Receive Interrupt 1 Status
19
R1T2
IR1 Transmit Interrupt 2 Status
18
R1T1
IR1 Transmit Interrupt 1 Status
17
U2R2
UART2 Receive Interrupt 2 Status
16
U2R1
UART2 Receive Interrupt 1 Status
15
U2T2
UART2 Transmit Interrupt 2 Status
14
U2T1
UART2 Transmit Interrupt 1 Status
13
U1R2
UART1 Receive Interrupt 2 Status
12
U1R1
UART1 Receive Interrupt 1 Status
11
U1T2
UART1 Transmit Interrupt 2 Status
10
U1T1
UART1 Transmit Interrupt 1 Status
9
SPR2
SPI Receive Interrupt 2 Status
4
SPR1
SPI Receive Interrupt 1 Status
3
SPT2
SPI Transmit Interrupt 2 Status
2
SPT1
SPI Transmit Interrupt 1 Status
1
ACT
Action Bit
0
This bit is an action bit. The value of this bit is written to
any selected bits during register writes. Bits to be written