LSI Logic Confidential
10-14
Host Async Master Interface
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Chip Select Configuration Register
Personality-dependant
Address = 0x6F024 - 0x6F04C
D
31
Data transfer acknowledge type. If clear, M_DTACK will
be used for transfer acknowledge. If set, M_WAIT will be
used. Reset to zero.
TA
[30:29]
Data transfer acknowledge control, one of the following:
M
28
Model select. If clear, SRAM mode cycles will be run. If
set, 68K mode cycles will be run. See
. Reset
to zero.
B
27
Burst-enable. If set, burst reads will be allowed to this CS
as in
. If clear, bursts will be broken up into
single-beat transfers. Reset to zero.
X
26
Multiplexed address enable. If set, an address multiplex
cycle will be run as in
. Reset to one.
AS
[25:24]
Address setup time, corresponding to AS in
Reset to three.
31
30
29
28
27
26
25
24
23
22
19
18
D
TA
M
B
X
AS
A
CS
DS
15
14
11
10
7
6
0
DS
BH
BD
DT
00
Transfer is self-paced. (Reset value)
01
Reserved
10
Transfer is device-paced with asynchronous
acknowledge (input is clocked twice)
11
Reserved