LSI Logic Confidential
SIO Register Descriptions
15-91
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
UART1 Line Status Register (UART1_LSR)
UART2 Line Status Register (UART2_LSR)
Offset = 0xBE0114 / 0xBE0194
Read only
Default = 0x60000000
This register provides status information about the UART transmitter and
receiver to the host processor. After module reset, the TEMT and THRE
bits are high (meaning the transmitter is idle) and all other bits are low
(meaning no receiver error conditions exist).
ERRBT
Error Bit
31
This bit is always low in non-FIFO mode. In FIFO mode,
it is set when there is at least one parity, framing, or
break indication in the FIFO.
This bit is reset when the Line Status Register is read,
and there are no subsequent errors in the FIFO.
TEMT
Transmitter Empty
30
1 = Both the Transmitter Holding Register and the Trans-
mitter Shift Register are empty (transmitter idle condi-
tion).
THRE
Transmit Holding Register Empty
29
1 = The UART is ready to accept a new character for
transmission. This bit causes the UART to issue an inter-
rupt to the host processor when the THRE bit is set in the
Interrupt Enable register.
The bit is set by the UART internal logic when the data
to be transmitted is shifted from the Transmit Holding
Register to the Transmit Shift Register.
This bit is cleared when the system loads data into the
Transmit Holding Register.
In FIFO mode, this bit is reset when at least one byte is
written to the FIFO, and it is set when the transmit FIFO
is empty.
31
30
29
28
27
26
25
24
23
16
ERR BT
TEMT
THRE
BI
FE
PE
OE
DR
RSVD
15
0
RSVD