LSI Logic Confidential
16-6
Clock Control and Power Management
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
self clearing bit which must be set by software at least
1 ms after any internal clock frequency change (including
starting the internal clock PLL on reset). The SDRAM
stop bit can be cleared 10 us after the resetDLL bit is set.
SDRAM activity can resume after the SDRAM stop bit is
read as zero. The internal clock frequency should not be
set below 81 MHz, or DRAM timing violations may occur.
N
[4:2]
See above. This field is reset to 0x4.
P
1
See above. Default value equals 1.
resetDLL
0
See above. Default value equals 0.
Video Output Clock Control Register
Memory Space Address: 0xC2000C
VinSrc27
9
If set, the Video Input 1 Clock pin is divided by two before
being applied to the PLLs. This bit should be set if the
external Video Input 1 Clock pin is 27 MHz, otherwise it
is assumed to be 13.5 MHz. After power up, this bit is 1.
VideoOut PLL Src
[8:7]
Specifies the video output PLL clock source as shown
below. If the source is internal or video input 1 clock, then
the video out clock pin becomes an output of the video
output clock. This field is reset to two.
31
10
9
8
7
6
4
3
0
VinSrc27 VideoOut PLL Src
N
P