LSI Logic Confidential
Pin Description
18-69
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Table 18.35 308 BGA Alphabetical Pin List (Cont.)
VO_D[14]
E3
VO_D[15]
F4
VO_D[1]
H2
VO_D[2]
H3
VO_D[3]
H4
VO_D[4]
G1
VO_D[5]
G2
VO_D[6]
G3
VO_D[7]
F1
VO_D[8]
F2
VO_D[9]
G4
VSS
H8
VSS
H9
VSS
H10
VSS
H11
VSS
H12
VSS
H13
VSS
J8
VSS
J9
VSS
J10
VSS
J11
VSS
J12
VSS
J13
VSS
K8
VSS
K9
VSS
K10
VSS
K11
VSS
K12
VSS
K13
VSS
L8
VSS
L9
VSS
L10
VSS
L11
VSS
L12
VSS
L13
VSS
M8
VSS
M9
VSS
M10
VSS
M11
VSS
M12
VSS
M13
VSS
N8
VSS
N9
VSS
N10
VSS
N11
VSS
N12
VSS
N13
VSS_2.5
K16
VSS_A
A8
VSS_A
A9
VSS_A
C8
VSS_A
C9
VSS_DLL
T17
VSS_DLL
U17
VSS_RREF
B11
VSS_X
C10
XVDD
A11
Signal
Pin
Signal
Pin
TCK
D8
TDI
C7
TDO
B7
TMS
B6
TRST
D7
VDD_1.8
D4
VDD_1.8
E10
VDD_1.8
E12
VDD_1.8
J5
VDD_1.8
M5
VDD_1.8
T9
VDD_1.8
T10
VDD_1.8
U4
VDD_2.5
C16
VDD_2.5
D15
VDD_2.5
D17
VDD_2.5
J16
VDD_2.5
L16
VDD_3.3
D5
VDD_3.3
E4
VDD_3.3
E9
VDD_3.3
E11
VDD_3.3
K5
VDD_3.3
L5
VDD_3.3
T4
VDD_3.3
T11
VDD_3.3
T12
VDD_5
U5
VDD_A
B8
VDD_A
B9
VDD_A
D9
VDD_A
D10
VDD_DLL
U15
VDD_DLL
U16
VDD_RREF
D11
VI_CLK[0]
A5
VI_D[2]
B2
VI_D[3]
C3
VI_D[4]
C2
VI_D[5]
D3
VI_D[6]
C4
VI_D[7]
B3
VI_D[8]
A2
VI_D[9]
A1
VI_VSYNC[0]
C1
VO_CLK
H1
VO_D[0]
J4
VO_D[10]
E1
VO_D[11]
F3
VO_D[12]
E2
VO_D[13]
D1
VO_D[14]
E3
VO_D[15]
F4
VO_D[1]
H2
VO_D[2]
H3
VO_D[3]
H4
VO_D[4]
G1
VO_D[5]
G2
VO_D[6]
G3
VO_D[7]
F1
VO_D[8]
F2
VO_D[9]
G4
VSS
H8
VSS
H9
VSS
H10
VSS
H11
VSS
H12
VSS
H13
VSS
J8
VSS
J9
VSS
J10
VSS
J11
VSS
J12
VSS
J13
VSS
K8
VSS
K9
VSS
K10
VSS
K11
VSS
K12
VSS
K13
VSS
L8
VSS
L9
VSS
L10
VSS
L11
VSS
L12
VSS
L13
VSS
M8
VSS
M9
VSS
M10
VSS
M11
VSS
M12
VSS
M13
VSS
N8
VSS
N9
VSS
N10
VSS
N11
VSS
N12
VSS
N13
VSS_2.5
K16
VSS_A
A8
VSS_A
A9
VSS_A
C8
VSS_A
C9
VSS_DLL
T17
VSS_DLL
U17
VSS_RREF
B11
VSS_X
C10
XVDD
A11
VDD_3.3
K5
VDD_3.3
L5
VDD_3.3
T4
VDD_3.3
T11
VDD_3.3
T12
VDD_5
U5
VDD_A
B8
VDD_A
B9
VDD_A
D9
VDD_A
D10
VDD_DLL
U15
VDD_DLL
U16
VDD_RREF
D11
VI_CLK[0]
A5
VI_D[2]
B2
VI_D[3]
C3
VI_D[4]
C2
VI_D[5]
D3
VI_D[6]
C4
VI_D[7]
B3
VI_D[8]
A2
VI_D[9]
A1
VI_VSYNC[0]
C1
VO_CLK
H1
VO_D[0]
J4
VO_D[10]
E1
VO_D[11]
F3
VO_D[12]
E2
VO_D[13]
D1
VO_D[14]
E3
VO_D[15]
F4
VO_D[1]
H2
VO_D[2]
H3
VO_D[3]
H4
VO_D[4]
G1
VO_D[5]
G2
VO_D[6]
G3
VO_D[7]
F1
VO_D[8]
F2
VO_D[9]
G4
VSS
H8
VSS
H9
VSS
H10
VSS
H11
VSS
H12
VSS
H13
VSS
J8
VSS
J9
VSS
J10
VSS
J11
VSS
J12
VSS
J13
VSS
K8
VSS
K9
VSS
K10
VSS
K11
VSS
K12
VSS
K13
VSS
L8
VSS
L9
VSS
L10
VSS
L11
VSS
L12
VSS
L13
VSS
M8
VSS
M9
VSS
M10
VSS
M11
VSS
M12
VSS
M13
VSS
N8
VSS
N9
VSS
N10
VSS
N11
VSS
N12
VSS
N13
VSS_2.5
K16
VSS_A
A8
VSS_A
A9
VSS_A
C8
VSS_A
C9
VSS_DLL
T17
VSS_DLL
U17
VSS_RREF
B11
VSS_X
C10
XVDD
A11
VCC_1.8
M5
VDD_1.8
T9
VDD_1.8
T10
VDD_1.8
U4
VDD_2.5
C16
VDD_2.5
D15
VDD_2.5
D17
VDD_2.5
J16
VDD_2.5
L16
VDD_3.3
D5
VDD_3.3
E4
VDD_3.3
E9
VDD_3.3
E11
VDD_3.3
K5
VDD_3.3
L5
VDD_3.3
T4
VDD_3.3
T11
VDD_3.3
T12
VDD_5
U5
VDD_A
B8
VDD_A
B9
VDD_A
D9
VDD_A
D10
VDD_DLL
U15
VDD_DLL
U16
VDD_RREF
D11
VI_CLK[0]
A5
VI_D[2]
B2
VI_D[3]
C3
VI_D[4]
C2
VI_D[5]
D3
VI_D[6]
C4
VI_D[7]
B3
VI_D[8]
A2
VI_D[9]
A1
VI_VSYNC[0]
C1
VO_CLK
H1
VO_D[0]
J4
VO_D[10]
E1
VO_D[11]
F3
VO_D[12]
E2
VO_D[13]
D1
Signal
Pin
Signal
Pin
Signal
Pin
NC pins are not connected.