LSI Logic Confidential
A-4
Register Listing
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
SPI DMA Transmit Address Pointer2 Register
(SPI_TX_ADDR_PTR2_ADDR)
SPI DMA Transmit Address Pointer3 Register
(SPI_TX_ADDR_PTR3_ADDR)
SPI DMA Transmit Address Pointer4 Register
(SPI_TX_ADDR_PTR4_ADDR)
SPI DMA Transmit Control Register (SPI_TX_CONTROL_REG_ADDR)
SPI DMA Transmit Status Register (SPI_TX_STATUS_REG_ADDR)
SPI Receive Header Register (SPI_RXHDR)
SPI Shift Register (SPI_SHIFT)
UART1 / UART2 Divisor Latch LSB Register (DLL)
UART1 / UART2 Divisor Latch MSB Register (DLM)
UART1 / UART2 Divisor Latch MSB Register (DLM)
UART1 / UART2 Interrupt Enable Register (IER)
UART1 / UART2 Receive Buffer Register (RBR)
UART1 / UART2 Transmit Holding Register (THR)
UART1 DMA Receive Address Pointer1 Register
(UART1_RX_ADDR_PTR1_ADDR)
UART1 DMA Receive Address Pointer2 Register
(UART1_RX_ADDR_PTR2_ADDR)
UART1 DMA Receive Address Pointer3 Register
(UART1_RX_ADDR_PTR3_ADDR)
UART1 DMA Receive Address Pointer4
(UART1_RX_ADDR_PTR4_ADDR)
UART1 DMA Receive Control Register
(UART1_RX_CONTROL_REG_ADDR)
UART1 DMA Receive Status Register
(UART1_RX_STATUS_REG_ADDR)
UART1 DMA Transmit Address Pointer1 Register
(UART1_TX_ADDR_PTR1_ADDR)
UART1 DMA Transmit Address Pointer2 Register
(UART1_TX_ADDR_PTR2_ADDR)
UART1 DMA Transmit Address Pointer3 Register
(UART1_TX_ADDR_PTR3_ADDR)
UART1 DMA Transmit Address Pointer4 Register
(UART1_TX_ADDR_PTR4_ADDR)
UART1 DMA Transmit Control Register
(UART1_TX_CONTROL_REG_ADDR)
UART1 DMA Transmit Status Register
(UART1_TX_STATUS_REG_ADDR)
UART1 External Clock / Prescaler Register (UART1_PRESCALER)
UART1 FIFO Control Register (FCR)
UART1 Hardware Flow Control Register (UART1_HW_FLOW_CTRL)
UART1 Interrupt Enable Register / Divisor Latch MSB Register
(UART1_IER0_DLM1)
UART1 Interrupt Identification / FIFO Control Register (UART1_IIR_FCR) 15-85
UART1 Interrupt Identification Register (IIR)