LSI Logic Confidential
17-26
JTAG Boundary Scan
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
573
V4
ATAPI_ADDR[4]
[IN/OUT]
574
–
Control
[CTRL]
575
W3
ATAPI_ADDR[0]
[IN/OUT]
576
–
Control
[CTRL]
577
Y2
ATAPI_DATA[15]
[IN/OUT]
578
–
Control
[CTRL]
579
Y1
ATAPI_RESET
[OUT]
580
–
Control
[CTRL]
581
W2
ATAPI_INTRQ
[IN]
582
–
Control
[CTRL]
583
V3
ATAPI_DIOR
[OUT]
584
–
Control
[CTRL]
585
W1
ATAPI_DMARQ
[IN]
586
–
Control
[CTRL]
587
V2
ATAPI_ADDR[1]
[IN/OUT]
588
–
Control
[CTRL]
589
U3
ATAPI_ADDR[3]
[OUT]
590
–
Control
[CTRL]
591
V1
ATAPI_ADDR[2]
[OUT]
592
–
Control
[CTRL]
593
U2
ATAPI_DATA[14]
[IN/OUT]
594
–
Control
[CTRL]
595
T3
ATAPI_IORDY
[IN]
Table 17.2
Boundary Scan Chain Cells (Cont.)
Cell
Pin
Name
Type