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DMN-8600 DVD Recorder System Processor

A-1

LSI Logic Confidential

Chapter A
Register Listing

Async Master Status/Time-out Register

10-18

Audio DMA In Status Register

12-17

Audio DMA Out Status Register

12-18

Audio IEC-958 Status Out1 Register

12-17

Audio IEC-958 Status Out2 Register

12-17

Audio Input Clock Control Register

16-8

Audio Input Control Register

12-3

Audio Output Clock Control Register

16-9

Audio Output Control Register

12-8

Audio Status In 0 Register

12-16

Audio Status In 1 Register

12-16

Audio Status Out Register

12-16

Chip Select Configuration Register

10-14

Chip Select Configuration Registers

10-12

DVD Control Register

14-5

External DRAM Configuration Register

13-10

GPIO Value Register

10-17

Host Address Register (32-Bit Mode)

8-21

Host Address Register (for LE = 0 in 16-Bit Mode)

8-21

Host Address Register (for LE = 1 in 16-Bit Mode)

8-21

Host Control Register

8-12

Host Data Register (16-Bit Mode for LE = 0)

8-19

Host Data Register (16-Bit Mode for LE = 1)

8-19

Host Data Register (32-Bit Mode)

8-19

Host DMA Configuration Register

8-22

Host DMA Data Register

8-17

IDC Clock Register (IDC_CLOCK)

15-39

IDC Control Register 1 (IDC_CONTROL1)

15-32

IDC Control Register 2 (IDC_CONTROL2)

15-40

IDC DMA Receive Address Pointer 1 Register
(IDC_RX_ADDR_PTR1_ADDR)

15-47

IDC DMA Receive Address Pointer 2 Register
(IDC_RX_ADDR_PTR2_ADDR)

15-48

IDC DMA Receive Address Pointer 3 Register
(IDC_RX_ADDR_PTR3_ADDR)

15-48

IDC DMA Receive Address Pointer 4 Register
(IDC_RX_ADDR_PTR4_ADDR)

15-49

IDC DMA Receive Control Register (IDC_RX_CONTROL_REG_ADDR)

15-45

Summary of Contents for DMN-8600

Page 1: ... DMN 8600 DVD Recorder System Processor TECHNICAL MANUAL J u l y 2 0 0 2 Preliminary 3 LSI Logic Confidential ...

Page 2: ...sume any responsibility or liability arising out of the application or use of any product described herein except as expressly agreed to in writing by LSI Logic nor does the purchase or use of a product from LSI Logic convey a license under any patent rights copyrights trademark rights or any other of the intellectual property rights of LSI Logic or third parties Copyright 2001 2002 by LSI Logic C...

Page 3: ...s and managers who are evaluating the processor for possible use in a system Engineers who are designing the processor into a system Organization This document has the following chapters and appendixes Chapter 1 Overview defines DMN 8600 features and introduces its main applications Chapter 2 Application Example describes the common user interface shared by all DMN 8600 applications and provides a...

Page 4: ...gisters Chapter 11 Video Interface gives an extended description to the video interface includes registers Chapter 12 Audio Interface gives an extended description to the audio interface includes registers Chapter 13 SDRAM Interface gives an extended description to the SDRAM interface includes registers Chapter 14 Bitstream I O Storage Port gives an extended description to the bitstream I O interf...

Page 5: ...46 00 DMN 8100 Advanced Multiformat A V Processor for Video Peripheral Applications Technical Manual Document number DB14 000217 01 Galileo CE Development Board Preliminary User s Guide Document number DB15 000229 01 Galileo Light Galileo LT Development Board Advance User s Guide Document number DB15 000240 00 Conventions Used in This Manual The first time a word or phrase is defined in this manua...

Page 6: ...ers assigned to signals and part pro ductized as DMN 8600 August 15 2001 TD10 1017 Rev 0 20 Added register extended interface descriptions and AC DC information August 30 2001 TD10 1017 Rev 0 21 Special Edition September 18 2001 TD10 1017 Rev 0 22 Special Edition 2nd Edition October 2 2001 DB14 000198 00 Preliminary Edition January 31 2002 DB14 000198 01 Preliminary 2 Edition Chapter 15 expanded e...

Page 7: ...iption 4 1 RISC Engine 4 1 4 2 Video Processing 4 1 4 2 1 Motion Estimation Coprocessor 4 2 4 2 2 Video DSP Coprocessor 4 2 4 3 Audio Processing 4 2 4 4 Interfaces and I O 4 3 4 4 1 Host Interface 4 4 4 4 2 Bitstream Storage Interface 4 5 4 4 3 IEEE 1394 Interface 4 6 4 4 4 Video Interface 4 6 4 4 5 Audio Interface 4 7 4 4 6 SDRAM Interface 4 7 4 4 7 Serial I O Interface 4 8 4 4 8 JTAG Interface T...

Page 8: ...DMA 8 4 8 2 Async Slave Interface Transfer Modes 8 4 8 2 1 Transfer Mode A 8 4 8 2 2 Transfer Mode B 8 5 8 3 Async Slave WRITE and READ Protocols 8 5 8 3 1 I Mode WRITE and READ Operations 8 5 8 3 2 I Mode Incoming Transfers 8 5 8 3 3 I Mode Outgoing Transfers 8 6 8 3 4 M Mode WRITE and READ Operations 8 7 8 3 5 M Mode Incoming Transfers 8 7 8 3 6 M Mode Outgoing Transfers 8 8 8 4 Host DMA Read Wr...

Page 9: ...ter DMA External Address Register Cbus 0x6F014 8 27 8 8 3 Master DMA NextAddress Register Cbus Addr 0x6F004 8 28 8 8 4 Master DMA StopAddress Register Cbus Addr 0x6F008 8 28 8 8 5 Master DMA BaseAddress and LimitAddress Registers Cbus Address 0x6F00C and 0x6F010 8 28 Chapter 9 Secondary Bitstream Interface 9 1 WRREQ 0 9 3 9 1 1 Bitstream Output Outgoing Transfers BRSD 1 9 3 9 1 2 Bitstream Input I...

Page 10: ...10 4 2 Transfer Acknowledge Mode 10 5 10 4 3 Timing Parameters 10 7 10 4 4 Burst Transactions 10 8 10 4 5 Device Paced Transfers 10 8 10 4 6 Multiplexed Address Cycles 10 10 10 5 Chip Select Configuration Registers 10 11 10 6 Interrupt GPIO Configuration and Value Registers 10 15 10 7 Async Master Status Time Out Register 10 17 10 8 Async Master SPARC Error Address Register 10 19 Chapter 11 Video ...

Page 11: ...12 21 12 6 2 FRFORM 1 12 22 12 6 3 FRFORM 2 12 23 12 6 4 FRFORM 3 12 23 12 6 5 FRFORM 4 12 24 12 6 6 FRFORM 5 12 24 12 6 7 FRFORM 6 12 25 12 6 8 FRFORM 7 12 26 Chapter 13 SDRAM Interface 13 1 DRAM Address Map 13 6 13 2 DRAM Address Field Description 13 6 13 3 Supported Number of Simultaneous Banks 13 7 13 4 SDRAM Initialization 13 8 13 5 SDRAM Refresh 13 9 13 6 External SDRAM Configuration Registe...

Page 12: ...10 15 2 3 SPI Clocking 15 11 15 2 4 SPI Transfer Host Polled Mode 15 12 15 2 5 SPI Programming Examples 15 12 15 2 6 Other Applications 15 15 15 2 7 SPI Programming Guidelines 15 15 15 3 IDC Interface 15 16 15 4 SIO UART Interface 15 18 15 4 1 UART Data Frame 15 18 15 4 2 Baud Rate Generator 15 18 15 5 SIO Register Descriptions 15 19 15 5 1 Interrupt Hierarchy 15 20 15 5 2 SIO Top Level DMA Engine...

Page 13: ...ng 18 20 18 2 5 CD Interface Timing 18 26 18 2 6 IDC Interface Timing 18 27 18 2 7 Audio Timing 18 30 18 2 8 UART Interface Timing 18 31 18 2 9 Video Interface Timing 18 32 18 2 10 IR Interface Timing 18 35 18 2 11 JTAG Interface Signal Timing 18 36 18 2 12 ATAPI AC Timing 18 38 18 2 13 SD Interface Timing 18 41 18 2 14 SPI Interface Timing 18 43 18 2 15 1394 Timing 18 44 18 2 16 SBP Interface Tim...

Page 15: ... 8 2 I Mode WRITE 8 6 8 3 I Mode READ 8 7 8 4 M Mode WRITE 8 8 8 5 M Mode READ 8 9 8 6 Host DMA Target Transfers 8 9 9 1 Secondary Bitstream Port SBP 9 2 9 2 Bitstream Port Outgoing Transfers with WRREQ 0 POL 1 and BSRD 1 9 3 9 3 Bitstream Port Incoming Transfers with WRREQ 0 POL 1 and BSRD 0 9 4 9 4 Outgoing FRAME Transfers 9 5 9 5 Incoming FRAME Transfers 9 6 9 6 Circular Buffer 9 7 10 1 Async M...

Page 16: ...ace Input Signal Formats 14 13 15 1 IR Interface Protocol 15 2 15 2 NCR IR Protocol 15 5 15 3 Philips RC 5 Protocol 15 6 15 4 SPI Block Diagram 15 8 15 5 32 Bit SPI Data Transfer Format 15 10 15 6 Inter Byte Timing Relationship 15 10 15 7 IDC Interface Data Transfer Protocol 15 17 15 8 UART Data Frame 15 18 15 9 Connections Between INTR_STATUS_ADDR and SIO_DMA_IRQ Registers 15 29 15 10 SPI Inter B...

Page 17: ...erface AC Timing 18 31 18 26 AC Timing for Video Input Stream at VI_CLK 0 18 32 18 27 AC Timing of Video Output at VO_CLK 18 34 18 28 IR Interface Timing 18 35 18 29 JTAG Interface Timing Diagram 18 37 18 30 ATAPI DMA AC Timing 18 38 18 31 ATAPI PIO Read and Write Timing 18 40 18 32 SD Interface Timing 18 42 18 33 32 Bit SPI Data Transfer Format 18 43 18 34 SBP Signal Level Parameters 18 44 18 35 ...

Page 19: ... 15 1 IR Waveform Register Value Relationship 15 2 15 2 Alignment of Transmit Data in SDRAM 15 7 15 3 Alignment of Receive Data in SDRAM 15 7 15 4 Priority Mode Select 15 24 15 5 Legal Target ID Values 15 25 15 6 Status Register Events 15 34 15 7 Bit bang Mode Bit to SPI Signal Mapping 15 63 15 8 SPI Transfer Modes 15 64 15 9 CSSL Bit to Chip Select Mapping 15 67 15 10 Number of Bits Sent Dependin...

Page 20: ...e Slave Timing Parameter 18 27 18 18 IDC Interface Master Timing Parameter 18 29 18 19 Audio Input Output AC Timing Parameters 18 30 18 20 UART Interface AC Timing 18 32 18 21 Video Input Stream AC Timing Parameters at VI_CLK 0 18 33 18 22 Video Out Clock Source 18 33 18 23 Video Output AC Timing Parameters at VO_CLK 18 34 18 24 IR AC Timing Parameters 18 36 18 25 JTAG Interface AC Timing Values 1...

Page 21: ...ly Relying on its internal host processor the DMN 8600 delivers leading performance for advanced image processing techniques such as deinterlacing and noise reduction by using motion compensation algorithms in combination with other features allowing delivery of the highest quality MPEG 1 MPEG 2 and DV compressed images The DMN 8600 can also be used as a powerful audio processor that encodes audio...

Page 22: ...nd a complete set of host and I O interfaces This architecture balances hardware that has been optimized for performance critical functions at the bit and pixel operations level with firmware that has been optimized for performance and scalability This balance delivers the flexibility needed to cut time to market and lower development cost See Table 1 1 Table 1 1 DMN 8600 Features Summary Video A ...

Page 23: ...e IDS inter device serial Port 2 channels Outputs Quad IDS ports 8 channels Resolutions 16 to 24 bits sample I O Serial Dual UARTs IEEE1394 Link SPI IR IR Blaster IDC Parallel ATAPI DVD SD SBP System Host 16 32 bit generic host interface or internal host Graphics 2D 24 bit RGB 8 bit alpha channel OSD flicker filter and video scaler Encryption decryption CPRM CPPM CSS 5C via 1394 Watermark detectio...

Page 24: ...multaneous encoding and decoding in MPEG 2 MP ML format simultaneous decoding to MPEG 2 MP ML and transcoding to DV25 multi angle view decoding DV25 to MPEG 2 with zero delay preview CD DA to MP3 transcoding as well as IEEE1394 transport stream muxing and demuxing The DMN 8600 also supports video recorders with hard disk drives and optical recorder drives in the same system with independent scramb...

Page 25: ...r appliance with analog time shift based on a DMN 8600 Figure 2 1 System Block Diagram for a DMN 8600 Based Advanced DVD Recorder Appliance The only major components needed to complete the design are 8 to 64 Mbytes SDRAM TV tuner Analog video encoder and decoder DMN 8600 RISC CPU 56 K Modem Modem DAA POTS IR Serial GPIO SDR DDR SDRAM 1394 Phy 1394 FP Control Front Panel Display Keypad Encoder Vide...

Page 26: ... attach DVD RAM or other read writeable DVD drives in dual loader configuration mode or in combination with a hard disk drive The DMN 8600 is able to record a single input either from a TV tuner the IEEE1394 link or the ATAPI interface in MPEG 1 or MPEG 2 format Similarly it is capable of decoding any of these formats including DVD Audio and sending the result to the video and audio DACs The built...

Page 27: ...for audio video and graphics data with a 32 bit data bus for support of 8 to 64 Mbytes of external SDR or DDR SDRAM SGRAM or FCRAM The DMN 8600 supports multiple external interfaces One video input and one video output interface to external ITU R BT 656 601 video decoder and encoder chips Dual port IDS inter device serial TDM time division multiplexed audio input and quad port IDS TDM audio output...

Page 28: ...8600 Internal Architecture Diagram 8 Video DSP and Memory Audio Interface Video Interface Motion Estimator and Memory Memory Controller SDRAM SGRAM Array Host Interface 2 Port 4 Port S PDIF 8 16 16 32 Storage Interface 1394 Link Interface SIO SPARC Processor Core SPARC Processor Core I Cache Data Memory Cache Audio DSP and Memory Host and Graphics CBus 64 32 I Cache Data Memory Cache Audio DSP and...

Page 29: ...ocessing and high level control flow and decision making tasks for video processing Optionally they can also perform 2D graphics and host functions The SPARC processors have a programmable scalable architecture that includes an internal 16 Kbyte instruction cache and an internal configurable 16 Kbyte data memory cache Data memory is used instead of a data cache when the software needs predictable ...

Page 30: ...off loads the SPARC processors Its 64 Kbyte data memory is double buffered two banks to allow concurrent DMA and DSP operations Some of the functions that the DSP coprocessor performs include Detelecine Activity measures Motion compensation Adaptive temporal and de interlace filtering Linear filtering decimation DCT IDCT discrete cosine inverse discrete cosine transforms up to 12 bits Quantization...

Page 31: ...e load and store operations and the multiply and accumulate operations 4 4 Interfaces and I O The DMN 8600 s connections to the outside world are summarized in Figure 4 1 The following subsections briefly describe each corresponding interface Figure 4 1 DMN 8600 System I O Diagram DMN 8600 IEEE1394 Link Host DDR SDR SDRAM DRAM LINK Bitstream Storage GClk 27 MHz or 13 5 xtal SIO ATAPI DVD SD CD SBP...

Page 32: ...torage interface is in ATAPI mode and SD_DATA 7 0 SBP_DATA 7 0 when the storage interface is in SD mode The limited master is primarily intended to support an external PROM accessed independently of the host processor Consequently it only supports one chip select with self paced cycles The host interface provides three distinct functions Local SDRAM access Internal register access Compressed data ...

Page 33: ...ate the header of the 2048 byte pack and perform DVD descrambling on scrambled sectors The resulting data is sent to the SDRAM using the DMA interface CD is a serial low level interface to the DSP on consumer electronics CD DA optical loaders Low bit rate 1 5 MHz CD DA CD ROM sector input coming from the ATAPI or a CD drive s bit serial interface is directly streamed to SDRAM where the DMN 8600 pe...

Page 34: ...ined in isochronous packets IPs The DMN 8600 filters the packets by matching channel ID s and performs 1394 descrambling on the scrambled data In case of MPEG 2 transport streams the DMN 8600 performs descrambling on the data scrambled with 5C encryption Software is responsible for transport section processing and demultiplexing For output DMA channels transfer data from SDRAM to the IEEE 1394 int...

Page 35: ...A D or AES SPDIF devices An externally or internally generated clock provides bit serial clocking of the data coming from an external ADC pair An externally or internally generated frame sync provides synchronization of frames Frames are organized as two samples per frame The four serial audio output ports send uncompressed 16 to 24 bit digital audio to external audio DACs or S PDIF devices An ext...

Page 36: ...internal bus as well as to a DMA channel so they can be used either as programmed I O or with DMA transfers The UARTs operate in full duplex mode UART1 supports synchronous communication as well as hardware flow control using the RTS CTS pins Note UART1 is not available when the external host port is configured in embedded Host plus Limited Master mode The SPI Serial Peripheral Interface port prov...

Page 37: ...erface Test Access Port The Joint Test Action Group JTAG interface includes a 5 pin port as outlined in IEEE standard 1149 1 The JTAG interface provides for boundary scan testing utilizing a multiplexor and latches on every pin of the DMN 8600 device that can be forced to a known state The actual data that is latched depends on multiplexor functions controlled by the TAP test access port controlle...

Page 39: ...tecture Figure 5 1 C Ware Architecture This architecture is layered starting with the Component layer Components abstract the hardware and provide access via a set of standardized APIs The next layer up is the Flow Control layer Flow controllers build complete functions such as a DVD encode function In this case the flow controller controls the video and audio capture the encoding and the storage ...

Page 40: ... market while increasing the ability to leverage a common platform across different products and the ability to be able to upgrade products Support for an external generic host 16 or 32 bit is provided through a set of generic host APIs All components and flow controllers provided by LSI Logic are fully optimized for performance and code compactness Note The DMN 8600 shares its API with LSI Logic ...

Page 41: ... external physical interface to the DMN 8600 Figure 6 1 shows a diagram of the DMN 8600 with all external interface signals grouped together Table 6 1 provides the pin name pin number type and description of each signal Multiplexed pins are selected by some combination of DMN 8600 input pins using MCONFIG 2 0 and for Bitstream I O only a control register All other interface pins have dedicated sig...

Page 42: ... 22 M_A 21 6 M_D 15 0 M_A 5 1 M_UWE M_UDS M_RD WR M_LWE M_OE M_LDS M_ALE M_WAIT M_DTACK SD_DATA 7 0 SD_SECSTART SD_CLK SD_RDREQ SD_WRREQ SD_ACK SD_ERROR CD_DATA CD_LRCK CD_BCK CD_C2PO ATAPI_RESET ATAPI_DATA 15 0 ATAPI_ADDR 4 0 ATAPI_DIOW ATAPI_DIOR ATAPI_INTRQ ATAPI_IORDY ATAPI_DMARQ ATAPI_DMAACK SBP_DATA SBP_CLK SBP_REQ SBP_RD SBP_ACK SBP_FRAME SIO_SPI_CLK SIO_SPI_MOSI SIO_SPI_MISO SIO_SPI_CS 3 0...

Page 43: ...yield the internal processing and audio video clocks CLKX B10 O Connected to other pin of 13 5 MHz crystal This pin should be unconnected if an LVTTL clock signal is connected to CLKI CLKO DAC A12 O The output of the internal 13 5 MHz crystal oscillator or output of a train of digital pulses controlled by register TCdacCtl The function is selected by the clock control register PLL_BYPASS A7 I Bypa...

Page 44: ...log supplies These are isolated nets which supply power to each analog block in the design VDD_RREF D11 3 3 3 3 V analog power This is an isolated net which supplies power to the internal Bandgap block VDD_X A11 3 3 Isolated 3 3 V nominal crystal oscillator supply VSS H8 H9 H10 H11 H12 H13 J8 J9 J10 J11 J12 J13 K8 K9 K10 K11 K12 K13 L8 L9 L10 L11 L12 L13 M8 M9 M10 M11 M12 M13 N8 N9 N10 N11 N12 N13...

Page 45: ..._LREQ M1 O Link Request It makes the bus request to access the PHY layer BIO_LPS L4 O Link Power Status Indicates that the link is powered and functional It requests the PHY to disable or enable the PHY link interface BIO_LINK_ON K4 I Occurrence of a link on event BIO_PHY_CLK L1 I PHY_CLK is the 49 152 MHz clock supplied by the PHY device MCONFIG MCONFIG 1 0 Y16 M16 I These mode pins indicate the ...

Page 46: ...ower mode when the chip is put in a power down state SDRAM_CAS B17 O Active LOW SDRAM Column Address Strobe Connects directly to CAS inputs SDRAM_RAS B16 O Active LOW SDRAM Row Address Strobe Connects directly to RAS inputs SDRAM_DQM 3 0 G19 K20 L17 N17 O These pins are the byte masks corresponding to SDRAM_DQ 7 0 15 8 23 16 and 31 24 They allow for byte reads writes to SDRAM and connect gluelessl...

Page 47: ... compatible only All outputs are specified with a 25 pF load and 10 mA Drive VI_CLK 0 A5 I Video input clock VI_CLK 0 is the sample clock for video input stream 1 single stream Input data is sampled on the rising edge For 8 bit video input VI_CLK is twice the pixel clock frequency given the 4 2 2 I O format and should be 27 MHz for CCIR 601 format video Input capture is synchronized to EAV or SAV ...

Page 48: ... by the Yfirst bit in the video control register For 16 bit YCrCb video data luma and chroma samples are output on VO_D 7 0 and VO_D 15 8 pins respectively VO_CLK H1 I O Video Output Clock VO_CLK is the sample clock for video output The direction of VO_CLK is programmable Output data and control signals are driven on the rising edge if olckr is set otherwise they are driven on the falling edge For...

Page 49: ...LK is asynchronous to all other chip clocks This clock is internally generated and driven out AI_MCLKO A13 O Audio master input clock output for the internally generated master input clock AO_MCLKO B13 O Audio Master Output Clock output for the internally generated master output clock AI_D 1 0 D12 C13 I Audio Stream Input Data Up to four channels of serial audio data are clocked in from the AI_D p...

Page 50: ...sync master no UART1 SPI IRTX signals H_INT U7 O Host interrupt request open drain output This pin is shared with M_GPIO 0 H_RST W16 I Host Reset signal This signal is shared with M_RST H_DATA 31 16 W4 Y3 V5 W5 Y4 V6 Y5 Y6 U6 W6 V7 W7 Y8 Y7 V8 W8 I O Host interface data bus 31 16 H_DATA 31 30 slave pins are shared with M_CS 5 4 H_DATA 29 26 slave pins are shared with M_CS 3 0 H_DATA 25 21 slave pi...

Page 51: ...d IR transmit UART2 IR receive and IDC are still available The limited master is primarily intended to support an external PROM accessed independently of the host processor consequently it only supports one chip select with self paced cycles M_GPIO 5 0 Y9 Y10 W9 W10 Y13 U7 I O General purpose I O 5 0 These pins are shared with H_CS H_RD H_ADDR 2 0 and H_INT respectively M_RST W16 I Master Reset si...

Page 52: ...H_DMAREQ M_RD WR M_LWE U8 master mode V17 slave limited master mode O Master Lower Write Enable SRAM mode direction 68K mode M_RD WR is shared with H_RD WR when in master mode and shared with SIO_UART1_CTS when in slave limited master mode M_OE M_LDS Y15 master mode W17 slave limited master mode O Master OE SRAM mode Lower data strobe 68K mode Shared with IRTX2 when in slave limited master mode M_...

Page 53: ...both sync or async mode Multiplexed with ATAPI_IORDY If SD_CLK 1 then input data and control signals are sampled on the rising edge otherwise they are sampled on the falling edge SD_RDREQ V3 O The chip asserts SD_RDREQ to indicate that the internal buffer has available space and it is ready to perform a read SD_WRREQ 1 or that it will be reading data SD_WRREQ 0 Multiplexed with ATAPI_DIOR SD_WRREQ...

Page 54: ... and the DVD control register see description of DVD control register on page 14 5 ATAPI_RESET Y1 O The chip reset for connected ATAPI devices ATAPI_DATA 15 0 Y2 U2 T2 R2 R1 P2 N3 M4 N1 N2 N4 P1 P3 P4 R3 R4 I O ATAPI_DATA is the bidirectional data bus ATAPI_DATA 15 8 are shared with SBP_DATA 7 0 and ATAPI_DATA 7 4 are shared with SD_DATA 7 4 ATAPI_DATA 3 0 are shared with SD_DATA 3 0 and CD_CDPO C...

Page 55: ...Q U3 O SBP request for data transfer WrReq 0 or write transfer request WrReq 1 Active low if POL 1 otherwise active high SBP_RD V1 O SBP read write transfer WrReq 0 or read transfer request WrReq 1 Active low if POL 1 and WrReq 1 otherwise active high SBP_ACK V2 I Transfer of data acknowledged by system Active low if POL 1 otherwise active high SBP_FRAME W3 I O Indicates first byte of each frame S...

Page 56: ...ignal per pin MCONFIG 1 0 00 selects the SIO_UART1 signals listed below SIO_UART1_TX U20 O UART1 transmit Multiplexed with M_A 4 SIO_UART1_RX W19 I UART1 receive Multiplexed with M_CS 0 SIO_UART1_RTS V20 O UART1 request to send Multiplexed with M_A 3 SIO_UART1_CTS V17 I UART1 clear to send Multiplexed with M_WR UART2 As Serial I O pins SIO_UART2 pins are shared with up to one other signal per pin ...

Page 57: ...a In BST serial data chain input TMS B6 I Test mode select Controls state of test access port TAP controller TCK D8 I Test clock Boundary scan test BST serial data clock 1 I input O output OD open drain PU requires external pull up resistor Table 6 1 DMN 8600 Pin Descriptions Cont Name Pin No Type1 Description ...

Page 59: ...mory map for different configurations These configurations include SDRAM access and access to internal registers via the internal Control Bus CBus Section 7 1 Host Interface Address Mapping Section 7 2 SPARC Processor Address Mapping Section 7 3 Control Bus Address Mapping 7 1 Host Interface Address Mapping A 32 bit address is used to access either the SDRAM or the CBus registers as shown in Figur...

Page 60: ...epending on the system implementation 7 2 1 In System with an External Master Processor DMN 8600 SPARC processors boot from SDRAM the external master must load SPARC boot code into SDRAM via the DMN 8600 device s Host Interface Figure 7 2 shows the resulting memory map 0000_0000 10FF_FFFF 1000_0000 0FFF_FFFF 8000_0000 90FF_FFFF 9000_0000 8FFF_FFFF FFFF_FFFF 16 Mbyte CBus Space with Address Increme...

Page 61: ...2 2 In System with No External Master Processor DMN 8600 SPARC processors boot from an external ROM Figure 7 3 shows the resulting memory map 16 Mbyte CBus Space 256 Mbyte SDRAM Space FFFF_FFFF FF00_0000 FEFF_FFFF 8000_0000 9FFF_FFFF 9000_0000 8FFF_FFFF 256 Mbyte Master Space 256 Mbyte SDRAM Space 0000_0000 1FFF_FFFF 1000_0000 0FFF_FFFF 256 Mbyte Master Space Cached Accesses Uncached Accesses ...

Page 62: ... address space is divided into 256 regions of 16 K words each The resources in the Control Bus address space are the control registers status registers Audio Memory AMem and RISC memory Rmem A 24 bit address offset is used to index into the CBus space shown in Figures 7 1 through 7 3 Table 7 1 shows the assignments of these blocks to the various modules within the DMN 8600 device 16 Mbyte CBus Spa...

Page 63: ...FFFF Audio I O 0x06_0000 0x06_FFFF Host 0x07_0000 0x07_FFFF Reserved 0x08_0000 0x08_FFFF SBP Secondary Bitstream 0x09_0000 0x70_FFFF Reserved 0x80_0000 0x80_FFFF AMem 0x81_0000 0xBD_FFFF Reserved 0xBE_0000 0xBF_FFFF Serial I O UART IR SPI 0xC0_0000 0xC0_FFFF RMem 0xC1_0000 0xC1_FFFF Video DSP 0xC2_0000 0xC2_FFFF CLK Controller 0xC3_0000 0xC3_FFFF DSP DMem 0xC4_0000 0xC4_FFFF Video I O 0xC5_0000 0x...

Page 65: ... Section 8 6 Host Interface Registers Section 8 7 Host DMA Registers Section 8 8 Master DMA Registers The Host processor port is configured differently for different processors It supports the following general features 16 or 32 bit Host data bus Host DMA target WAIT and DTACK signalling for slow response time Separate or combined Read and Write strobes The DMN 8600 embedded host interface support...

Page 66: ... perform master mode DMA transfers this interface replaces either the Slave interface operating without an external host the master interface replaces the slave interface to allow use of the serial I O interfaces Serial I O interface shares pins with the storage interface with separate control signals used to allow dynamic arbitration between storage and master mode transfers In this configuration...

Page 67: ...nternal DMA channel is programmed to match the transfers being performed by the host Each interface is described in the following sections Bitstream IO Port Local DRAM External to DoMiNo Device E5 Bitstream FIFO 1 of 7 Select DMA H_DATA 31 16 H_DATA 15 0 H_ADDR 2 0 3 16 Host Interface Local Registers Internal Bus Host Interface Control Logic H_CS H_RD WR H_WR H_RD H_DTACK Multiplexed Mode Individu...

Page 68: ...e receives slave transfer requests from an external host and internally arbitrates the transfers The Host interface does not support burst transfers The slave interface provides a FIFO buffer between the internal DMA channel and the bitstream pins All internal DMA reads transfer data from the bitstream FIFO to SDRAM and internal DMA writes transfer data from SDRAM to the bitstream FIFO 8 2 Async S...

Page 69: ...t I mode the Host should perform a dummy read cycle to the Host Address Register address 0x4 using the RD strobe in the first Host access after reset In I mode the address is sampled when WAIT and DTACK are driven once WR or RD go LOW 8 3 2 I Mode Incoming Transfers Figure 8 2 shows an I mode write The sequence is as follows The Host drives the address and CS 1 and asserts WR 2 after the address a...

Page 70: ... shows an I mode read The sequence is as follows The Host drives the address on the A 2 0 bus and asserts RD 1 after the address is stable On the HIGH to LOW edge of RD 2 the DMN 8600 processor samples the address asserts WAIT and asserts DTACK from a 3 state level shaded area is 3 state to a HIGH level The DMN 8600 processor deasserts WAIT 3 and asserts DTACK after it drives the read data out on ...

Page 71: ...in is held HIGH throughout M mode In M mode the address is sampled when WAIT and DTACK are driven when CS goes LOW 8 3 5 M Mode Incoming Transfers Figure 8 4 shows an M mode write The sequence is as follows The Host drives the address and WR and asserts CS 1 after the address and WR 2 are stable The DMN 8600 processor asserts WAIT and deasserts DTACK 3 in response to a CS HIGH to LOW edge The proc...

Page 72: ...sor samples the Address and RD WR 1 on the HIGH to LOW edge of CS The processor asserts WAIT 2 and deasserts DTACK from a 3 state to HIGH level shaded area is 3 state in response to the HIGH to LOW transition of CS The DMN 8600 processor deasserts WAIT 3 and asserts DTACK after driving data out Deassertion of WAIT or assertion of DTACK causes CS 4 to be deasserted The DMN 8600 processor stops driv...

Page 73: ...egister is accessed using a standard host read or write no separate DMA acknowledge is used Figure 8 6 Host DMA Target Transfers To configure the DMA target register for little endian Host transfers set the LE bit in the Host Control register In this case data bytes are swapped when transferring data between SDRAM and the Host register The BSRD bit in the Host Configuration register controls the d...

Page 74: ... remaining space in the FIFO and additional data is still required to complete the DMA transfer Any data sent when H_DMAREQ is deasserted is ignored and lost 8 4 2 Outgoing Transfers from DMN 8600 Device When BSRD 1 in the Host Configuration register the Host receives bitstreams from the DMN 8600 device as follows H_DMAREQ is asserted when there is data in the bitstream FIFO H_DMAREQ is deasserted...

Page 75: ... multiplexed16 bit and DMA 16 bit I O mode or Mode C 16 bit and a separate 8 bit Primary Bitstream Port I O mode The LE bit in the Host Control Register selects between big endian and little endian byte ordering Table 8 2 Host Register Mapping 32 bits wide Address Big Endian Little Endian DATA 31 16 DATA 15 0 DATA 31 16 DATA 15 0 0x0 Read Version Register Write Ignored Read Host Control Write Host...

Page 76: ...e 0x60000 CBus LE LE Little Endian 12 If LE is set then host DMA transfers between SDRAM and the host DMA data register are byte swapped other wise they are not swapped Table 8 3 Host Register Mapping 16 bits wide Address Big Endian DATA 15 0 Little Endian DATA 15 0 0x0 Host Control Register Host Control Register 0x1 Version Register Ignore Writes Version Register Ignore Writes 0x2 Host Data Regis...

Page 77: ...icant half is at host address 0x2 and most significant half at address 0x3 1 Host DMA transfers between SDRAM and the Host DMA Data Register are byte swapped 0 They are not swapped H32 H32 11 A read writable bit that is set by the host processor if host slave transfers are 32 bits wide and cleared if host transfers are 16 bits wide If H32 is set host DMA transfers are 32 bit wide host DMA targets ...

Page 78: ...e flag that is set when the Video RISC core has entered the ERROR state This bit will remain set until cleared by software external reset or setting the Chip Reset bit 1 Send interrupt to RISC core 0 Cleared by software Vrst Video CPU Reset 5 A read writable bit that resets the DMN 8600 Video SPARC processor core and Video DSP Other units including SDRAM control ME processing video channel system ...

Page 79: ...table bit resets the SPARC core and Video DSP It does not reset other units such as the SDRAM controller ME video channel video SPARC video DSP and Host interface to allow debug access This bit is cleared by chip reset when no external host interface is present as determined by the Mode pins to allow the system SPARC processor to attempt booting from PROM It is set by reset when the host interface...

Page 80: ...1 Reset processor chip 0 Normal operation WrD 0 The value of this bit is written in the Host Control Register The field that needs to be written is indicated by a logic value 1 in that bit position A logic value 0 in that bit position indicates that the field is not updated Value to write to other Host Control Register bit fields 8 6 2 Version Register This 16 bit register indicates the silicon ch...

Page 81: ...32 is set Reads or writes to this register when the H_DMAREQ pin is not asserted are ignored 8 6 3 1 Reading the Host DMA Data Register Reading this register when H_DMAREQ is asserted transfers 16 or 32 bits from the internal bitstream FIFO to the host DMA channel and deasserts H_DMAREQ At the end of the read if additional data is available in the bitstream FIFO H_DMAREQ is reasserted 8 6 3 2 Writ...

Page 82: ...Address registers 8 6 4 1 16 bit Host Mode with LE 1 If LE is set in 16 bit Host mode the least significant 16 data bits are in the register at host address 0x2 and the most significant 16 data bits are in the register at host address 0x3 When performing a read to a new address read the 0x3 Host data register first followed by a read to 0x2 When performing a write to a new address write to the 0x3...

Page 83: ...er triggers a 32 bit read which also loads the 0x3 Host data register When performing a write to a new address in 32 bit mode the 0x3 data register should be written last Writing the 0x3 data register triggers a 32 bit write by combining the data with the 0x2 data register Writing the 0x2 Host data register triggers a write in 32 bit host mode however in 16 bit host mode only the host register is ...

Page 84: ... in the register at Host address 0x4 and the least significant 16 bits of the address are in the register at Host address 0x5 8 6 5 2 32 Bit Mode In 32 bit host mode the two 16 bit registers are combined into a single 32 bit register at address 0x4 LE has no effect in this case Only bits 28 0 of the address are used for the CBus SDRAM address Addresses outside the SDRAM and CBus space will be igno...

Page 85: ...ata 15 0 Host Space Address 0x5 Most Significant 16 Bits of Data 31 16 Host Space Address 0x4 Most Significant 16 Bits of Data 15 0 Host Space Address 0x5 Least Significant 16 Bits of Data 31 16 Only 29 Bits of Address Data Exist at 0x4 for 32 bit Mode Table 8 4 Auto increment Support of Host Address Registers Operation 16 Bit Interface 32 Bit Interface Read ADR 0x2 Autoincrement Autoincrement Rea...

Page 86: ...rated when a host DMA transfer completes otherwise no interrupt is generated If IE is clear no Host completion interrupt is generated Incoming transfers are complete when the value of the Host DMA Next Address register equals the value of the Host DMA Stop Address register and the DMA data has been written to SDRAM Outgoing transfers are complete when the value of Host DMA Next Address equals the ...

Page 87: ...until the GO bit reads as zero to ensure that the last data has been written to SDRAM During incoming transfers using the host DMA mode the host interface drops the last byte if the data was received after the GO bit was cleared by software Note The GO bit should be cleared only if necessary and read as zero before software changes the value of BSRD or any other host DMA register other than the St...

Page 88: ...erred The two least significant and the upper 4 bits of this register must be zero 8 7 3 Host DMA StopAddress Register CBus Address 0x60068 This register at control bus address 0x60068 specifies the transfer stop SDRAM address for host DMA data When the Next Address reaches the value in this register and the DMA data has been transferred to SDRAM or the system the DMA transfer is completed and the...

Page 89: ... DMA Base Address register value before transferring additional data The two least significant and the upper four bits of these registers must be zero 8 8 Master DMA Registers All master DMA registers are 32 bit CBus registers which are accessible to the SPARC core or Host Interface using 32 bit loads or stores 8 8 1 Master DMA Configuration Register Cbus Addr 0x6F000 This register at control bus ...

Page 90: ...e to begin master DMA transfers The GO bit is cleared by hardware after the transfer is completed Software that clears the GO bit when BSRD is clear flushes the remaining contents of the master DMA transfer FIFO to SDRAM and terminates the transfer without generating an interrupt Clearing the GO bit when BSRD is set outgoing transfer discards the remaining contents of the master DMA FIFO and termi...

Page 91: ...ing output by DoMiNo If BSRD is clear master DMA transfers will be written by the system BSRD should not be changed while the GO bit is set 1 DMN 8600 processor outputs the DMA data 0 System writes the master DMA transfers WRData WRITE Data 0 The value of this bit is written to any selected bits during host DMA configuration register writes Bits to be written are selected by placing a 1 in each de...

Page 92: ... for master DMA data When the Next Address reaches the value in this register and the DMA data has been transferred to SDRAM or the system the DMA transfer is completed and the GO bit is cleared This register can be reloaded while a DMA transfer is active to extend the length of a DMA operation In a normal operation this register should never be greater than or equal to the address value stored in...

Page 93: ...t control bus address 0xdF010 specifies the SDRAM address for the first byte after the master DMA buffer When the master DMA next address reaches the value in the master DMA limit address register it is reloaded with the master DMA base address register value before transferring additional data The two least significant and the upper four bits of these registers must be zero ...

Page 95: ...ion 9 4 FIFO and Buffer Operation Section 9 5 Secondary Bitstream Interface Registers As a separate bitstream port the secondary bitstream interface is a synchronous flow controlled 8 bit data port The secondary bitstream port pins are shared with the ATAPI interface pins As a result the secondary bitstream port is only available when the storage port is in SD mode Transfers are clocked from the r...

Page 96: ...y Bitstream port See Table 9 1 for transfer direction and active state details External Device SBP_CLK CLK SBP_ACK SBP_RD SBP_REQ SBP_DATA 7 0 SBP_FRAME DoMiNo SDRAM SBP Table 9 1 Secondary Bitstream Pin Configuration Bit Setting Pin Name BSRD 0 Incoming BSRD 1 Outgoing POL 0 POL 1 POL 0 POL 1 WRREQ 0 SBP_ACK active HIGH active LOW active HIGH active LOW SBP_REQ active HIGH active LOW active HIGH ...

Page 97: ...in the Secondary Bitstream Configuration register and the Secondary Next Address is not equal to the Secondary Stop Address to indicate the direction of the transfer When the system asserts SBP_ACK in a clock in which SBP_REQ is asserted the oldest byte of bitstream data is removed from the FIFO at the end of the clock and the next oldest byte if present in the FIFO is presented on the next clock ...

Page 98: ...ng at 148 5 MHz SBP_REQ will be asserted continuously This allows a non flow controlled transfer to be used if necessary Figure 9 3 shows incoming transfers to the bitstream port with WRREQ 0 POL 1 and BSRD 0 In the figure note that SBP_ACK and SBP_REQ are shown as active LOW The system drives SBP_DATA Figure 9 3 Bitstream Port Incoming Transfers with WRREQ 0 POL 1 and BSRD 0 When SBP_ACK is asser...

Page 99: ...he SBP_FRAME signal is asserted with the first byte of an incoming or outgoing packet and is deasserted with the next byte of the packet The size of Secondary Bitstream packets is specified by the PACKSIZE register 9 3 1 Outgoing FRAME Transfers Figure 9 4 shows outgoing transfers using SBP_FRAME Figure 9 4 Outgoing FRAME Transfers For outgoing FRAME transfers the following occurs SBP_FRAME is ass...

Page 100: ...transfers BSRD 0 the following occurs After each PACKSIZE byte is captured long packet incoming bytes are discarded until SBP_FRAME is asserted If SBP_FRAME is asserted before PACKSIZE bytes are captured Early Frame Zero bytes are inserted to fill out PACKSIZE bytes in the SDRAM preserving the packet boundary alignment in the SDRAM SBP_REQ is deasserted the cycle after Early Frame until zero stuff...

Page 101: ...ed within the one millisecond time constraint the partially filled buffer will be flushed to SDRAM The FIFO is flushed under two situations 1 There is no SDRAM access for one millisecond only the contents in the FIFO are flushed to SDRAM It is possible that a few bytes may remain in the buffer 2 Software clears the GO bit the contents in the Packet register are first moved into the FIFO the GO bit...

Page 102: ...s describes the Next Address Stop Address Base Address and Limit Address registers in detail with respect to the SBP 9 5 Secondary Bitstream Interface Registers All secondary bitstream interface registers are 32 bit CBus registers which are accessible to the SPARC core or Host interface using 32 bit loads or stores 9 5 1 Secondary Bitstream Configuration Register This register resides at memory sp...

Page 103: ...ignored on incoming not sent on outgoing IE 4 If IE is set a SBP interrupt is generated when a Secondary Bitstream DMA transfer is completed other wise no interrupt is generated If IE is clear no SBP interrupt is generated Incoming transfers are complete when the value of the Secondary Next Address register reaches the value of the Secondary Stop Address Register and the bitstream data has been wr...

Page 104: ...e GO bit after writing zero until the GO bit reads as zero to ensure that the last data has been written to SDRAM Note The GO bit should be cleared only if necessary and read as zero before software changes the value of BSRD or any other Secondary Bitstream DMA register other than the Stop Address register Clearing the GO bit by hardware or software resets the packet framing Software should set th...

Page 105: ...ress 0x080824 specifies the SDRAM address for secondary bitstream data When GO is set this register specifies the starting SDRAM address where secondary bitstream data will be transferred As bitstream data is transferred this register is updated to point to one byte after the last transferred byte in SDRAM This register is read by microcode to determine how many bytes of bitstream information have...

Page 106: ...r the beginning of the circular SDRAM buffer The Secondary Limit Address register at control bus address 0x080830 specifies the SDRAM address for the first byte after the buffer When the next address reaches the value in the Secondary Limit Address register it is reloaded with the secondary base address register value before transferring additional data The two least significant and the upper four...

Page 107: ...Registers Section 10 7 Async Master Status Time Out Register Section 10 8 Async Master SPARC Error Address Register The DMN 8600 async master interface has three pin configurations described below to optimize the total pin count for different package and system configurations One of three configurations is selected by the MCONFIG 1 0 pins The configuration pins must not change after reset 10 1 No ...

Page 108: ...ive and IDC are still available The master interface pins M_ADDR 21 6 M_D 15 0 are shared with ATAPI_DATA 15 0 pins when the storage interface is in ATAPI mode and SD_DATA 7 0 SBP_DATA 7 0 when the storage interface is in SD mode Since the master and ATAPI control lines are separate both may operate concurrently ATAPI cycles are round robin arbitrated with master interface cycles SD and secondary ...

Page 109: ...ions are independent of each other and can be mixed and matched as the system designer sees fit 10 4 1 Data Strobe Mode There are two types of data strobes 68K mode and SRAM mode The mode selection changes the functions of three pins as described in Table 10 1 below Figure 10 1 shows the basic operation of these two cycle types Table 10 1 Pin Functions in Different Modes 68K Mode SRAM Mode M_RD WR...

Page 110: ...ved Figure 10 1 Async Master Read and Write Cycles BH CSO DSO BDT BH DT CSO DSO DT BH CSO DSO DT BH CSO DSO BDT BH DT CSO DSO DT BH CSO DSO 68K Mode Read 68K Mode Write 68K Mode Burst Read SRAM Mode Read SRAM Mode Write SRAM Mode Burst Read DT M_A M_RD WR M_CS M_UDS LDS M_D M_DTACK M_A M_CS M_UWE LWE M_D M_DTACK M_OE ...

Page 111: ...rt later in the cycle to indicate that the device needs more time to finish the transaction The cycle is complete when the M_WAIT signal is deasserted For self paced transfers as shown in Figure 10 2 the choice of M_WAIT or M_DTACK affects only the assertion level and the pin used for the acknowledge signal The master waits a programmed amount of time before asserting M_DTACK or deasserting M_WAIT...

Page 112: ... Figure 10 2 Self Paced Async Master Cycles with M_WAIT BH CSO DSO BDT BH DT CSO DSO DT BH CSO DSO DT BH CSO DSO BDT BH DT CSO DSO DT BH CSO DSO M_A M_RD WR M_CS M_UDS LDS M_D 68K Mode Read 68K Mode Write 68K Mode Burst Read M_WAIT M_A M_CS M_UWE LWE M_D M_WAIT M_OE SRAM Mode Read SRAM Mode Write SRAM Mode Burst Read DT ...

Page 113: ... M_WAIT is driven LOW at the start of the cycle then brought HIGH for one clock before being 3 stated On a read cycle data is latched in at the clock cycle after M_DTACK is asserted or M_WAIT deasserted For device paced M_DTACK transfers see Section 10 4 5 Device Paced Transfers page 10 8 For device paced M_WAIT transfers this value indicates the amount of time to wait before sampling the M_WAIT p...

Page 114: ...er parameters are only used at the beginning and end of the entire burst as shown in Figure 10 1 or Figure 10 2 The DT parameter controls the delay associated with the first beat of the burst and BDT the delay for subsequent beats The fastest self timed burst uses DT BDT 0 and takes one bus time unit per beat With this timing M_DTACK would remain low for all of the beats going high for a single cy...

Page 115: ...The designer must be careful to ensure that the target device has deasserted M_DTACK before the next cycle samples it starting with the clock edge that asserts the data strobes otherwise it may cause premature termination of the following cycle Typically this requires an extension of the BH parameter Note that for device paced burst transfers the M_DTACK or M_WAIT line is sampled only for the firs...

Page 116: ...ycles The DMN 8600 multiplexes the middle address bits 21 to 6 on the Addr Data lines For these cycles the address bits are captured with an external latch An address latch enable pin M_ALE is provided to control the latch The address multiplexing feature is selectively enabled on a per chip select basis This allows the designer to have both large address space devices like Flash ROMs that use the...

Page 117: ... guarantee sufficient hold time for the latch due to loading on the Addr and Data busses for instance this hold time can be set to zero 10 5 Chip Select Configuration Registers The DMN 8600 has six chip select pins M_CS 5 0 Each of these chip selects are controlled by a pair of 32 bit chip select configuration registers 0x6F020 0x6F024 0x6F028 0x6F02C 0x6F030 0x6F034 0x6F038 0x6F03C 0x6F040 0x6F04...

Page 118: ...8 Base Address 31 16 Base address of this chip select In DoMiNo the most significant 4 bits are zero Reset value is zero Size 11 8 Chip select size Controls size of chip select region in power of two sizes The Base Address parameter must be a multiple of this size as well Valid values are 0000 Chip select disabled 0001 Region is 64K 0010 Region is 128K 0011 Region is 256K 0100 Region is 512K 0101 ...

Page 119: ...ect region from user mode causes a host error inter rupt with status set in the Host Timeout register Reset to zero Type 3 0 Personality module for this chip select In DoMiNo the value is always zero which is the suggested ID of the async master module Note When a master range address with no M_CS pin selected occurs on a SPARC read the cycle is aborted and a data access exception trap is induced ...

Page 120: ...l be run If set 68K mode cycles will be run See Figure 10 2 Reset to zero B 27 Burst enable If set burst reads will be allowed to this CS as in Figure 10 2 If clear bursts will be broken up into single beat transfers Reset to zero X 26 Multiplexed address enable If set an address multiplex cycle will be run as in Figure 10 4 Reset to one AS 25 24 Address setup time corresponding to AS in Table 10 ...

Page 121: ...2 For device paced transfers this is the delay before sampling the M_DTACK M_WAIT input see Figure 10 3 Reset to 63 Note If the personality dependant register is written by software in the middle of a master will be used to complete the current bus cycle before using the new timing parameters 10 6 Interrupt GPIO Configuration and Value Registers The Interrupt GPIO Configuration register at control...

Page 122: ...falling edge after the level is reset will cause a new interrupt to be generated The most significant bit of each 4 bit field is a write enable Writes to the Interrupt GPIO configuration register will only update fields which have the write enable bit set to one Any fields that have a 0 write enable bit during register writes remain unchanged 31 24 23 20 19 16 15 12 11 8 7 4 3 0 Reserved GPIO 5 Mo...

Page 123: ...e selected by placing a 1 in each desired location as the register is written Any bit positions that contain a 0 during register writes remain unchanged Value is written to selected bits 10 7 Async Master Status Time Out Register This register at control bus address 0x6F018 specifies the async master error status and the time out interval for self paced master mode cycles The time out interval to ...

Page 124: ...nterrupt Master DMA completion interrupt handlers should check this register to see if the DMA transfer completed normally Async Master Status Time out Register Memory Space Address 0x6F018 VidSPARC MErr 19 Set when multiple VidSPARC errors occur before the register is cleared SysSPARC MErr 18 Set when multiple SysSPARC errors occur before the register is cleared DMA MErr 17 Set when multiple DMA ...

Page 125: ...except for the Master Timeout Interval field As a consequence the only way to clear the status fields and the MErr fields of this register is to read the register Any software routing that polls the Master Timeout Interval field also must handle the Error condition if applicable This register is reset to 0 10 8 Async Master SPARC Error Address Register This register at control bus address 0x6F01C ...

Page 127: ...deo input port and a video output port Figure 11 1 shows the data flow for the video input port The input port captures 8 bit digital video from ITU R 6561 parallel D1 or low cost video decoder chips such as the Philips SAA7111 Figure 11 1 Video Input Channel Data Flow 1 ITU R 656 refers to the ITU R BT 656 standard formerly known as CCIR 656 Decoder Interface Video In Dither Statistics Luma and C...

Page 128: ...h software specified coefficients and luma and chroma temporal filtering This combined with 4 2 2 to 4 2 0 conversion eliminates the need for chroma preprocessing and eliminates the need for loading previous data and storing current data in luma preprocessing The DMN 8600 computes statistics during capture including DC measurements horizontal activities for strips and same parity IT detection scor...

Page 129: ...optionally passed through an interpolating 4 tap 8 phase horizontal filter The video output channel can convert from 4 2 0 to 4 2 2 on the fly using a 2 tap field or frame filter with software specified coefficients The video input channel can also perform on the fly color correction with software specified coefficients The video output channel supports a separate PIP video layer and a separate OS...

Page 130: ...and DVD format pixel control data To provide scaling flexibility subpicture decoded data is output to SDRAM with color compositing and scaling performed by the VDSP 11 1 Video Output Format Figure 11 3 shows the video output format for each interlaced field The DMN 8600 hardware supports one blanking and one normal data window per field However microcode can implement multiple normal data windows ...

Page 131: ...rts both interlaced and progressive video streams However this document describes only interlaced streams Figure 11 4 shows the single video stream Data Window 3 EAV Black Black Output Border Color Data Window 1 Black Xsize 3 Ysize Right Pel Offset 1 Left Pel Offset 1 Window 1 Top Offset Window 1 Bottom Offset Window 2 Top Offset Active Bottom Offset Note 1 Pels cannot be captured within the restr...

Page 132: ...e implemented using reserved 0x00 and 0xFF code sequences within the video field Figure 11 5 ITU R BT 656 Timing 11 3 Video Control Register The Video Control Register is used to control a variety of features as described in the description below A read modify write cycle must be used when accessing this register Interleaved Single Stream Odd Field Even Field 4 Clocks Horizontal Blanking Active Vi...

Page 133: ...progressive capture of progressive input One chroma output line will be produced for every two chroma input lines with successive chroma output lines being stored in chroma field 0 The FRC bit setting must be the same for all windows in the same field VCP 28 Vertical chroma phase If set when GoI is set then the input window is bottom field otherwise it is top field for chroma decimation purposes I...

Page 134: ...and queue A transfer is loaded into the queue each time the GoI2 bit is set by software A command is removed from the queue each time the transfer completes This bit can be used by software to poll for when to load the next command Polling is typically used for short transfers 10 microseconds and interrupts are used for longer transfers VCD 24 If set when GoI is set by software then the associated...

Page 135: ...d If ITS is also clear no accesses are performed to the previous field buffer in SDRAM If set when GoR is set by software then the associated rescale window will output data in interleaved YCbYCr or CbYCrY format depending on PYfirst otherwise the rescale window will output data in separate luma chroma format If set when Go0 is set by software then the associated output window will read data in in...

Page 136: ...ust be programmed to 0 CC 18 If set when GoR is set by software then the associated rescaling operation will perform color correction on the rescaled results before storing to memory Color correction can only be performed on 4 2 2 data bit 7 of the scale i instruction or data which is vertically interpolated to 4 2 2 data VCD bit set If set when GoO is set by software then the associated output wi...

Page 137: ...ciated output window will be processed by the horizontal and vertical video output filter If clear then the associated output window will bypass the horizontal video output filter and will not be clamped at this stage If set when GoR is set by software then the associated rescale operation will be processed by the horizontal rescale filter If clear then the associated rescale operation will bypass...

Page 138: ...f set and PV is set when GoR is set by software then the associated rescale window will output data in interleaved YCbYCr format otherwise the rescale window will output data in CbYCrY format If set and PV is set when Go0 is set by software then the associated output window will read output data in interleaved YCbYCr for mat otherwise the output window will read output data in CbYCr format If set ...

Page 139: ... the video output without storing into SDRAM using the most recently stored values in the input data vertical range register Up to two video capture commands can be outstanding at any time The Echo bit remains set while there is at least one video input capture outstanding to allow software polling of completion The Echo bit must be set before the start of the capture window or a partial window ma...

Page 140: ...ning of field if OSync is set once the video input timing has been stable for two pairs of odd even fields or frames Gol 1 Set by microcode to queue up a video input stream 1 capture window using the most recently stored values in the input stream 1 data vertical horizontal and result range destination luma and chroma address and row column offset registers Up to two video capture commands can be ...

Page 141: ...5 0 are 3 stated independent of any active output transfer If clear these pins are driven by DoMiNo 3 tating allows other video sources to share the video output bus At reset this bit is set to avoid contention on the output pins The reset sequence can clear this bit if DMN 8600 is the only driver This bit should not be changed while an output transfer is active or pending YFirst 20 If set the vid...

Page 142: ... output fields between synchronization points must align the beginning of an odd output field with each odd input field When Osync is set the number of clocks between input odd fields be held constant for two odd even input pairs ahead of valid output through the end of output to ensure stable output sync Also VOE must be asserted on all clocks that VIE is asserted Osync should not be changed whil...

Page 143: ...ated Note that rescale instructions pending in the DSP instruction queue will not complete after GoR is cleared by Stop Software can do a syncdsp before setting Stop or it can set GoR again later or reset the video SPARC This bit should always be set to 0 in DoMiNo P In 14 If set progressive input the beginning of a video input frame of both input streams is defined to be the EAV sequence where th...

Page 144: ...ted in the RLE pixel data of an RLE window including the start of pixel data for a scan line not aligned to a byte boundary or the pixel data is longer than the RLE window width This bit remains set until cleared by software VSP 7 If set input video vertical sync first line in field or frame of each input stream is determined by assertion of the VI_VSYNC 0 pin and the EAV F bit is ignored If clear...

Page 145: ...hardware if the current input field interlaced of input stream 1 is odd This information comes from the most recent EAV SAV F bit value on the video input 1 Early 1 Set if an EAV code where the F bit toggles ProgIn clear or the V bit toggles to zero ProgIn set occurs between the top and bottom lines of the window This bit remains set until cleared by software BOvr 0 Set by the hardware when excess...

Page 146: ...pect ratio pixels to 720H resolution output Pre M 26 If set when GoOSD is set specifies that software has pre multiplied the OSD RGB values in the associated OSD window by the alpha value If not set when GoOSD is set specifies that OSD RGB values should be multiplied by alpha before blending with the video layer Alpha Mode 25 24 When GoOSD is set specifies the alpha mode of the associated OSD wind...

Page 147: ...he first active video line data from the PIP window otherwise data from the video input stream 1 echo window overlays the video output window if active otherwise the background color RLEalpha cannot set in the same output field or frame as a VideoRGB RLEAlpha is not implemented in the first version of DoMiNo This bit should always be zero RLEInt 15 The completion of an RLE window generates an RLE ...

Page 148: ...ly by the scale factor amount ScaleV 8 7 Specifies the vertical scale factor for OSD data OSD data is scaled by duplicating pels vertically by the scale factor amount Programming Note 2x vertical scaling for interlaced output is best achieved by displaying both fields of OSD data in each field that is both the top set and the bottom set Bott 6 If set bottom field data is displayed in OSD windows a...

Page 149: ...f set when the GoOSD bit is set by microcode the associated OSD window will apply flicker filtering to primary and secondary OSD data otherwise flicker filtering will not be applied and only primary OSD data is displayed for that window This bit should not be changed while an OSD transfer is active or pending This bit is ignored when video is used as a graphics layer or if both Top and Bottom are ...

Page 150: ...SD Vertical Range OSD Horizontal Range and OSD Data Address registers Up to two OSD windows can be outstanding at any time The GoOSD bit must be set before the start of the OSD window Typically it is set from the video field or OSD interrupt handler The GoOSD bit remains set while there is at least one video output transfer outstanding to allow software polling for completion Clearing this bit is ...

Page 151: ...s Section 12 6 Audio Frame Formats For the 8600 audio interface four channels of audio input and eight channels of audio output are supported with common input and output clocks AI_D 1 0 Incoming serial stream audio data AI_SCLK Serial clock for stream audio input AO_SCLK Serial clock for audio output AO_D 3 0 Outgoing serial stream audio data The 8600 uses incoming and outgoing frame sync signals...

Page 152: ... of the next output sample or frame as specified by the Audio Output Control register 12 1 1 MCLK The audio input master clock is internally generated according to Ain Master in the clock control register The internally generated audio input master clock is output on the AI_MCLKO pin The audio output master clock is internally generated according to Aout Master in the clock control register The in...

Page 153: ...y write cycle should be used when accessing this register Audio Input Control Register Cbus Address 0x50004 Iclkr 25 Specifies the clock polarity for audio input stream 1 signals Input signals are sampled on the opposite edge that output signals are driven If set audio input stream 1 serial data and frame sync input AI_D 3 0 AI_FSYNC as an input are clocked on the rising edge of the AI_SCLK input ...

Page 154: ...ponds to a 256xFs master clock An IBclk of zero and ITim clear corresponds to a 128xFs master clock as used with ADCs which perform clock doubling for 48Khz sample rates An IBclk value of two and ITim clear corresponds to a 384xFs master clock Programming note This field should be programmed at least one frame time before setting the GoI bit Stop 21 Setting this bit halts audio input and output pr...

Page 155: ...mming note This field should be programmed at least one frame time before setting the GoI bit 0 14 13 These bits must be programmed to 0 ISync 12 11 If Isync is set to zero the input stream audio bit clock AI_SCLK and frame sync AI_FSYNC pins are inputs for externally generated frame timing If Isync is set to one AI_SCLK and AI_FSYNC are outputs and frame timing is derived from the input master cl...

Page 156: ...mended for the CS4227 for optimum performance If clear and Frform is not one then the internally generated timing of each input sample is 32 clocks If Frform is one then the internally generated timing of each input sample is 16 clocks Programming note This field should be programmed at least one frame time before setting the GoI bit IS32 8 If set input stream 1 samples in memory occupy 32 bits ot...

Page 157: ...if a second transfer completes before the first interrupt is taken When the interrupt is taken the count of outstanding interrupts is decremented by one Res Reserved 3 IQF 2 A read only bit which is set when there are two outstanding DMA transfers in the audio input stream 1 command queue A transfer is loaded into the queue each time the GoI bit is set by software A command is removed from the que...

Page 158: ...V958 23 Value of V bit during IEC958 transfer R958 22 21 Specifies the rate of I958 sample output relative to audio output stream 1 samples as shown in the table below This allows the I958 output to run at a subsampled rate typically 44 1 kHz or 48 kHz of the main audio output as required in DVD Audio Programming note This field Set Clear Description Set by software Queue up a new transfer max of ...

Page 159: ...chip to be muxed with the internally generated stream OBclk 17 15 Specifies the divisor ratio of the audio output bit clock AO_SCLK from the audio output master clock as shown in the table below I9S32 14 If set IEC958 output samples in memory occupy 32 bits otherwise they occupy 16 bits If 32 bit samples are selected then only the upper 24 bits of the sample are transmitted in each output subframe...

Page 160: ...data is transferred on the I958 output pin with the usual IEC958 framing IEC958 timing is generated from the master audio clock and is adjusted so that one one half or one fourth of an IEC958 sample is transmitted in each audio output sample time as determined by the OTIM bits and R958 field The length of audio output 1 transfers with I958 set must correspond to an even number of IEC958 samples IE...

Page 161: ...here is no other timing reference to delineate sample boundaries Frform transfers four 16 bit word per frame additional bits are discarded on input and zero on output For output frames the first word is the left lowest channel number sample the second word is the most significant 16 bits of the status out register the third word is the right output sample and the fourth word is the least significa...

Page 162: ...it Fits in Output 1 0 16 16 Perfect fit 1 1 32 16 Only upper 16 bits of data are used 2 Not implemented in DoMiNo 0 3 4 0 0 16 32 Fits into first 16 bits of output the remaining 16 bits zero filled 0 3 4 0 1 16 64 Fits into first 16 bits of output the remaining 48 bits zero filled 0 3 4 1 0 32 32 Perfect fit 0 3 4 1 1 32 64 Fits into first 32 bits of output the remaining 32 bits zero filled 5 7 0 ...

Page 163: ...in memory occupy 32 bits otherwise they occupy 16 bits See second table in FrForm OClkr 7 If set audio output stream serial data and frame sync AO_D 3 0 and AO_FSYNC are clocked on the falling edge of the AO_SCLK input otherwise they are clocked on the rising edge Programming note This field should be programmed at least one frame time before setting the Go bit ChCnt 6 5 The number of audio output...

Page 164: ...his bit can be used by software to poll for when to load the next command Polling is typically used for short transfers 10 microseconds and interrupts are used for longer transfers 0 1 This bit must be programmed to 0 GoO 0 Set by microcode to queue up an audio output stream DMA transfer using the most recently stored values in the Audio Output DMA address and length registers The goO bit remains ...

Page 165: ...YNC pin independent of the state of the GoO bit 12 4 Audio Status Registers The DMN 8600 processor can also input output audio status information Usually the status input output provides status information to an audio codec connected to the processor or delivers status words from an audio codec to the processor For the DMN 8600 three registers are used for status input and three for status output ...

Page 166: ...its of the Audio Status In 0 register Status data from AI_D 1 is loaded into the least significant 16 bits of the Audio Data is captured only when the associated input DMA is capturing These registers are typically used to capture codec status Audio Status Out Register Memory Space Address 0x050014 Audio Status Out 31 0 Audio Status Out Contains the data clocked in control words in Frform one Frfo...

Page 167: ...s in each IEC 958 block The 32 bits in IEC 958 Status 2 Out are clocked out on the first 32 subframe two status bits in each IEC 958 block Bit 0 of each register corresponds to the first subframe in the block Updates to the status registers are not transmitted on the IEC 958 until the start of the next block to avoid corrupting partially transmitted status information Programming note When changin...

Page 168: ...is read before the next associated outstanding audio transfer is completed to avoid losing the time stamp Programming note software can use Audio PTS to detect bad sclk rates 12 5 Audio Address and Length Registers The DMN 8600 processor provides registers containing length and SDRAM address information for audio stream transfers For DoMiNo four registers are used for length and two for SDRAM addr...

Page 169: ... 0x05003C that contains the SDRAM address for an audio output stream transfer This register is initially written by the SPARC processor as an audio output transfer is being configured The contents are undefined after the transfer begins This register is part of a two level command queue that is advanced each time the GoO bit is set by software Reading or writing the Audio Output DRAM Address regis...

Page 170: ...output transfers with I958 set must correspond to an even number of IEC958 samples 12 6 Audio Frame Formats The DMN 8600 processor supports seven audio frame formats Table 12 1 lists these formats with the products they support To select the format needed by the application the host must issue the Audio Configuration command defined in the DMN 8600 Programming Reference Manual The number of sample...

Page 171: ... 7 right justify the sample in the frame When an output sample s memory size is 16 bits and the output timing is 32 clocks per sample 16 leading zeros are pre pended When an output sample s memory size is 16 bits and the output timing is 64 clocks per sample 48 leading zeros are pre pended When an output sample s memory size is 32 bits and the output timing is 64 clocks per sample 32 leading zeros...

Page 172: ...additional bits are discarded on input FRFORM 1 uses a pulse frame sync FSYNC signal On output FSYNC is HIGH for one clock and then goes LOW until the next frame Figure 12 3 On input the HIGH to LOW transition is ignored Figure 12 4 FRFORM 1 clocks in the left status information from the AI_D 3 0 pins to the Audio Status In 0 and 1 Registers as shown in Figure 12 1 Note that the right status infor...

Page 173: ...tted per frame sync FSYNC cycle FRFORM 3 uses a Left HIGH Right LOW frame sync that is the Left sample is present when FSYNC is HIGH and the Right sample is present when FSYNC is LOW The FSYNC transition occurs at the first bit of each sample The transition of FSYNC from LOW to HIGH and HIGH to LOW defines the beginning or end of each sample SCLK FSYNC Audio 16 Bits 1 Frame 16 Bits 16 Bits 16 Bits...

Page 174: ...ition occurs one clock cycle before the first bit of each sample The transition of FSYNC from LOW to HIGH and HIGH to LOW defines the beginning or end of each sample Figure 12 5 FRFORM 3 Audio Frame Definition Figure 12 6 FRFORM 4 Audio Frame Definition 12 6 6 FRFORM 5 Figure 12 7 shows the FRFORM 5 audio frame format In this format two 16 bit audio samples are transmitted per frame sync FSYNC cyc...

Page 175: ...rmat two 18 bit audio samples are transmitted per frame sync FSYNC cycle FRFORM 6 uses a Left HIGH Right LOW frame sync that is the Left sample is present when FSYNC is HIGH and the Right sample is present when FSYNC is LOW The FSYNC transition occurs one clock after the last bit of each 18 bit external sample The transition of FSYNC from LOW to HIGH and HIGH to LOW defines the beginning or end of...

Page 176: ...M 7 uses a Left HIGH Right LOW frame sync that is the Left sample is present when FSYNC is HIGH and the Right sample is present when FSYNC is LOW The FSYNC transition occurs one clock after the last bit of each 20 bit external sample The transition of FSYNC from LOW to HIGH and HIGH to LOW defines the beginning or end of each sample Figure 12 9 FRFORM 7 Audio Frame Definition Right Justified SCLK ...

Page 177: ...l Registers Section 13 8 SDRAM Arbitration and Throttle Registers Section 13 9 SDRAM Timing The DMN 8600 processor uses a 32 bit memory interface that supports up to 64 Mbytes of DRAM The DRAM memory uses two to four 16 bit wide SDR DDR DRAMs or one to two 32 bit wide SDR DDR DRAMs capable of running at 150 MHz 2 5 V 3 3 V SDRAM_RAS and SDRAM_CAS latency and cycle times are programmable to allow f...

Page 178: ...uantity Config Total MG SDR SDRAM 512 K x 32 b x 4 Banks 1 or 2 stacked 8 16 Mbytes SDR SDRAM 1 M x 16 b x 4 Banks 2 or 4 stacked pairs 16 32 Mbytes SDR SDRAM 2 M x 16 b x 4 Banks 2 or 4 stacked pairs 32 64 Mbytes DDR SDRAM 512 K x 32 b x 4 Banks 1 or 2 stacked 8 16 Mbytes DDR SDRAM 512 K x 32 b x 8 Banks 1or 2 stacked 16 32 Mbytes DDR SDRAM 1 M x 32 b x 4 Banks 1or 2 stacked 16 32 Mbytes DDR SDRA...

Page 179: ...A 11 0 CLK WE DQ 15 0 DQ 32 16 DQM0 DQM1 RAS CAS CS CKE LDQM UDQM LDQS UDQS DQ 15 0 A 11 0 CLK WE DQM2 DQM3 RAS CAS CS CKE LDQM UDQM LDQS UDQS DQ 15 0 A 11 0 CLK CKE LDQM UDQM LDQS UDQS CLK WE DQ 15 0 DQ 32 16 DQS0 DQS1 RAS CAS CS DQ 15 0 A 11 0 WE DQS2 DQS3 MADDR 14 MADDR 15 SDRAM_CLK1 SDRAM_CLK0 CLK CLK CLK CLK 8M x 16 4 banks 8M x 16 4 banks 8M x 16 4 banks 8M x 16 4 banks VREF VREF VREF VREF B...

Page 180: ... SDRAM_DQ 31 0 SDRAM_CKE SDRAM_CLK 1 Processor RAS CAS CS CKE LDQM UDQM DQ 15 0 A 11 0 CLK WE DQ 15 0 DQ 32 16 DQM0 DQM1 RAS CAS CS CKE LDQM UDQM DQ 15 0 A 11 0 CLK WE DQM2 DQM3 DQM2 DQM3 RAS CAS CS CKE LDQM UDQM DQ 15 0 A 11 0 CLK CKE LDQM UDQM CLK WE DQ 15 0 DQ 32 16 DQM0 DQM1 RAS CAS CS DQ 15 0 A 11 0 WE MADDR 14 MADDR 15 8M x 16 4 banks 8M x 16 4 banks 8M x 16 4 banks 8M x 16 4 banks BA 1 0 BA...

Page 181: ...nnections Using SDR SRAM SDRAM_RAS SDRAM_A 14 SDRAM_CAS SDRAM_WE SDRAM_CLK 0 SDRAM_A 10 0 SDRAM_DQM 3 0 SDRAM_DQ 31 0 SDRAM_A 12 11 SDRAM_CKE E5 Device RAS CAS CS CKE DM 3 0 DQ 15 0 A 10 0 CLK WE RAS CAS CS CKE DM 3 0 DQ 31 16 A 10 0 CLK WE SDRAM_A 15 SDRAM_CLK 1 2M x 32 SDRAM 4 banks 2M x 32 SDRAM 4 banks BA 1 0 BA 1 0 ...

Page 182: ...iption To support 64 Mbytes 16 Mwords with a 32 bit wide word requires 24 bits of word addressing The 7 to 9 LSBs are used to select word inside a page The bits above the column address bits are used to select banks 2 bits for 4 banks and 3 bits for 8 banks The bits above E5 Device RAS CAS CS CKE DM 3 0 DQS DQ 15 0 A 10 0 CLK WE RAS CAS CS CKE DM 3 0 DQS DQ 31 16 A 10 0 CLK WE CLK CLK 2M x 32 SDRA...

Page 183: ...e Bank Select pin connections for DDR based systems differ in the way the extended mode register EMR programming is defined in the DRAM chip on the board If the EMR is defined as BA1 BA0 Adr pins for the DRAM then the two bank select pins of DoMiNo need to be connected to the DRAM in order more significant DoMiNo BA pin to BA1 less significant DoMiNo BA pin to BA0 However if the EMR is defined as ...

Page 184: ... taken out of Stop mode by programming the Internal Clock Control register see Section 16 1 After reset CS and SDRAM_DQM will be held high and CKE will be low Once the above registers are programmed the DMN 8600 will initialize the DRAM using the following sequence For SDR Two precharge all banks commands are issued followed by two refresh commands before the mode register is programmed for normal...

Page 185: ...ermined by the CAS latency field CAS in the Exter nal DRAM Configuration register as loaded from the serial ROM Burst Type 3 The Burst type field will be set to 0 denoting Sequential accesses rather than Interleaved accesses between banks Burst Length 2 0 The Burst length field will be assigned a value of 011 denoting a burst length of eight DoMiNo will terminate bursts by issuing another read wri...

Page 186: ...30014 SD DDR 31 SDRAM DDR Indicates the type of external DRAM Not applicable to the embedded part 0 Single Data Rate SG SDRAM 1 DDR SG SDRAM Page Size 30 29 PAGE size All pages are 32 wide For 16 bit wide parts refers to the page size of a pair of parts The tile height is determined by this field 00 Page size is 32x128 Tile height is 8 this requires a bank count bit 22 of 8 01 Page size is 32x256 ...

Page 187: ...with page size of 512 words Drive Stren 21 Drive strength at the DRAM pins 0 Normal full drive 1 Half drive Last Data to Read 20 19 Last data of a read command delay This indicates how soon after the last data for a write a read command can be issued LtoF L 18 LtoF Last data from one data bus drivers to first data from another data bus driver This indicates the minimum number of dead clocks betwee...

Page 188: ...SDRAM 1 1 clock Typically for DDR ActiveP Latency 14 12 ActiveP latency tRAS specifies the minimum number of clocks between activate and precharge commands to the same bank The actual value is programmed_value 4 Prech Latency 11 10 Prech latency tRP specifies the minimum number of clocks between a precharge command and an activate command to the same bank The actual value is programmed_value 2 Act...

Page 189: ... nominal value for 150 MHz is 2340 clocks 2048 rows every 32 ms for SDRAMs and 1170 clocks 1024 rows every 8 ms for DDRs 13 7 SDRAM Control and Clock Control Registers As shown below the SDRAM Control and Clock Control Registers in the DMN 8600 processor set up the interface to SDRAM SDRAM Control Register Cbus Address 0x30000 Write Limit 15 0 A store by an incoming IPC target or any DMA transfer ...

Page 190: ... 23 16 DQSinTapSel specifies the delay from the DQS input strobe to input capture The delay is in units of 1 256 of the internal clock period InClkTapSel 15 8 For SDR DRAM InClkTapSel specifies the delay from the internal DoMiNoClock clock to the input capture For DDR dram this field specifies the delay from write data out to DQS out The delay is in units of 1 256 of the internal clock period OutC...

Page 191: ...am 1 Opposite Field Chroma frame chroma decimation 7 Video Stream 1 Capture Channel 8 1394 DMA 9 Secondary Bitstream Port DMA 10 ATAPI DMA 11 SMARTCARD_scd1MemReq 12 SMARTCARD_scd2MemReq 13 Audio Stream 1 Output Channel 14 Audio Stream 2 Output Channel 15 Audio Stream 1 Input Channel 16 Audio Stream 2 Input Channel 17 Audio IEC958 Output Channel 18 SIO DMA request 19 Async Master DMA 20 Video SPAR...

Page 192: ...er the previous request The priority of Host DMA requests are moved to the lowest priority for the number of clocks specified by the Host DMA throttle register after the previous request SDRAM Host DMA Throttle Register Cbus Address 0x3000C Host DMA Throttle Count 11 0 After a Host DMA request is asserted the internal host DMA throttle counter is set to the host DMA throttle count Subsequent host ...

Page 193: ... or SBP target bandwidth is not needed 13 9 SDRAM Timing The nominal output delay of SDRAM_CLK is matched to the delays of the other processor outputs to the SDRAMs including SDRAM_DQ The actual SDRAM_CLK output delay can be adjusted in microcode to lead the other processor outputs to the SDRAMs in increments of the processor CLK period divided by 256 This programmable lead time enables the SDRAM ...

Page 194: ...LSI Logic Confidential 13 18 SDRAM Interface Copyright 2001 2002 by LSI Logic Corporation All rights reserved specifically SDRAM_CLK so that read data can be captured independent of actual output delay ...

Page 195: ...reams on up to four channels in each direction Note The secondary BIO port described in Chapter 9 Secondary Bitstream Interface shares its pins with the ATAPI SD CD module In addition the BIO uses a DMA interface for communication with SDRAM This is similar to other modules in DoMiNo The BIO provides read write pointers base and limit registers for managing six SDRAM DMA ring buffers for ATAPI SD ...

Page 196: ...ing long sector data The ATAPI read and write cycles are described in Figure 14 1 The ATAPI register address is defined by the output pins CS0 CS1 DA2 DA1 and DA0 where CS0 is the most significant bit 14 1 1 Read Cycle The ATAPI read cycle starts when the ATAPI Interface receives the ATAPI_RD command from the host The ATAPI Interface subsequently puts the register address on the address bus and as...

Page 197: ... The ATAPI Interface follows by placing the register address on the address bus and asserting the ATAPI_DIOW signal time t1 later The ATAPI device can also initiate the wait cycle by driving the ATAPI_IORDY signal low before time tA During the wait cycle the ATAPI Interface keeps the register address write the data and the ATAPI_DIOW signal asserted until the ATAPI_IORDY signal becomes high 14 1 3...

Page 198: ...Interface asserts the ATAPI_DIOR signal to initiate the read operation and latch the data from the ATAPI device on the trailing edge of the ATAPI_DIOR signal This process repeats itself until the ATAPI device deasserts the ATAPI_DMARQ signal During the DMA write operation the ATAPI Interface asserts the ATAPI_DIOW signal and puts the data on the data bus to start the write operation The ATAPI devi...

Page 199: ...ed ATA register AtapiIEn 12 ATAPI Interrupt Enable When this bit is set and AtapiIntRq changes from 0 to 1 an ATAPI Completion interrupt is generated AtapiAddr 11 7 ATAPI Register Address This field corresponds to pins CS0 CS1 DA2 DA1 and DA0 CS0 is the most significant bit AtapiInt 6 ATAPI Interrupt Request Software can monitor the status of DoMiNo s ATAPI_INTRQ input pin by reading this read onl...

Page 200: ...ormation The result is written to SDRAM ATAPI_DESC_NO 0101 Use ATAPI interface to read a specified number of DVD sectors and don t descramble the data The result is written to SDRAM SD_DESC_BS 0110 Use SD interface to read a specified number of DVD sectors and descramble the data based on bitstream information The result is written to SDRAM SD_DESC_NO 0111 Use SD interface to read a specified numb...

Page 201: ...h Go 1 is ignored On reset Go 0 14 2 SD Interface The SD Interface is used to read data from and write data to the DVD drives The SD interface supports synchronous operations with the SD synchronous read and write timing diagrams shown in Figure 14 3 For the read operation the SD Interface asserts the read request signal SD_RDREQ when it receives the SD_DECS_BS or SD_DESC_NO command from the host ...

Page 202: ... first write data on the bus when SD_ACK is asserted The write data is latched by the SD device during the rising edge of the SD_ACK The SD Interface can place the next write data during the falling edge of the SD_CLK Figure 14 3 SD Interface Cycle 14 3 CD Interface Since the CD Interface supports several CD formats 32 bit 24 bit 24 bit IDS and 16 bit the host must program the SD CD Configuration ...

Page 203: ...d If the SrchCnt field in the SD CD Configuration register is zero the pass through CD DA mode is set and the CD Interface begins reading the CD data without a sector sync search 14 3 1 SD CD Configuration Register This register configures the SD CD interface The parallel SD interface can work in synchronous mode The serial CD interface consists of the following A bit clock pin CD_BCK used to samp...

Page 204: ...ite Request 0 An active SD_WRREQ pin indicates a write command and an active SD_RDREQ pin indicates a read command 1 An active SD_WRREQ indicates that there is a valid command which is a read if SD_RDREQ is active and a write if SD_RDREQ is not active EnSeSrt 19 1 Use the SD_SECSTART pin to mark the beginning of a sector instead of using header search Valid only for SD mode On input the BIO uses t...

Page 205: ... SD_CLK 1 SD data is sampled at the rising edge of SD_CLK SD Sync 10 1 SD interface is synchronous Note DMN 8600 supports synchronous SD only regardless of the value of this field It is still writable CDG Mode 9 8 Obsolete This field is used when WdLen 3 CD G Bit 8 indicates either CD G separate mode 0 or CD G composite mode 1 is used In CD G separate mode separate Frame Sync and Block Sync pins a...

Page 206: ...to report errors in each 128 byte block of data this bit doesn t affect the appendix DatOrd 2 0 MSbit first from bit 15 down to bit 0 1 LSbit first from bit 0 up to bit 15 WdLen 1 0 Number of bitclocks per phase of left right clock for CD 0 32 bit clocks 1 16 bit clocks 2 24 bit clocks 3 CD G 14 3 2 Valid Signal Formats The following signal formats are supported by DMN 8600 1 IDS 0 WdLen 0 DatOrd ...

Page 207: ...nnel 1 32 bit BCK MSB First Right Channel Low C2PO LSB First Data Latch Timing High 2 32 bit BCK MSB First Left Channel Low C2PO MSB First Data Latch Timing Low 0 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 Invalid Left Channel Upper Left Channel Lower Left Channel Right Channel Invalid MS LSB 3 24 bit BCK MSB First Right Channel Low C2PO MSB First Data Latch Timing High Upper Right Channel 10 11 12 1...

Page 208: ...8 9 10 11 12 13 14 15 1 0 Right Channel Left Channel Right Ch MSB Right Ch LSB 7 16 bit BCK MSB First Left Channel Low C2PO LSB First Data Latch Timing 11 12 13 14 15 Left Channel Right Channel 6 24 bit BCK MSB First Right Channel Low Data latch timing high Note no C2PO For This Format 0 2 1 3 4 5 6 7 8 9 10 11 13 14 15 Lower Right Ch Upper Right Ch Lower Left Ch Upper Left Ch Lower Right Ch Left ...

Page 209: ...ying the AV bitstreams to proper VBV buffers during vertical blanking interval VBI For output DMA channels transfer data from SDRAM to the 1394 and SD ATAPI interfaces In the case of 1394 isochronous output software prepares the proper 1394 time stamp in the packet header and multiplexes packets from different channels The isochronous packets optionally pass through the 1394 scrambler and channel ...

Page 211: ...ications port IDC two UARTs and two infrared interfaces IR The following are the major features of the SIO SPI interface with bit granularity transfer support Two UART interfaces one with hardware flow control support Two IR interfaces one with both IR blaster IR capture one with only IR blaster Block data transfer to and from the SDRAM DMA transfers managed by DMA engine SDRAM double buffers Oper...

Page 212: ... are shown in the following sections Figure 15 1 IR Interface Protocol SIO_IRRX sysclk SIO_IRTX Receive Tick Carrier Internal Signal Input Output Waveform Waveform 1 2 4 3 Internal Signal 5 7 6 Table 15 1 IR Waveform Register Value Relationship Reference Parameter Description Minimum Maximum sysclk System Clock 81 MHz 150 Mhz 1 MSPR IRTX Modulated Signal Pulse User can program overall period of IR...

Page 213: ...nal s pulse shape the pulse s period and pulse low width are programmed with the period programmed last Bit 26 of the Transmit Period register IR_MSPR is the Transmit Enable bit When programmed to one this bit indicates that the pulse shape values should be loaded immediately after the completion of the current pulse 3 CWP IRTX Carrier Wave Period User can program period of carrier waveform in uni...

Page 214: ... of ticks between falling edges of the input signal the duty cycle is determined by counting the number of ticks during which the incoming signal is high Note that the tick value is programmable from 1 to 32768 sysclk periods via the IR_RTP register Some protocols such as the NEC protocol allow for optimized processing of noisy inputs by prepending a start pulse of defined length to all valid tran...

Page 215: ...ing in to reveal more detail SIO_IRTX and SIO_IRRX are asynchronous The timing parameter values are under program control e g application specific 9 ms 2 25 ms 108 ms 58 5 76 5 ms 108 ms 18 36 ms 4 5 ms 27 ms 9 ms New Key Repeated Keypress 9 ms 4 5 ms 0 56 ms 1 125 ms 2 25 ms 0 1 0 1 0 0 1 0 Repeated Keypress 0 56 ms Repeated Keypress Carrier Waveform 9 ms or 0 56 ms 8 77 µs 26 3 µs Leader Code Cu...

Page 216: ...1 3 IR Programming Guidelines Using the DMA Engine with IR requires that data in SDRAM be word aligned and that it follow a particular format This is necessary because the DMA Engine actually reads writes two IR registers at once In non DMA mode in order to write an IR datagram two registers must be written sequentially MSPL and MSPR However the DMA Engine writes these two registers simultaneously...

Page 217: ... where the SPI controller is the bus master Table 15 2 Alignment of Transmit Data in SDRAM IR TX Data Address Data Address Data Address Data Address Data 1st Chunk x8000 MSPL 31 24 x8001 MSPL 23 16 x8002 MSPR 31 24 x8003 MSPR 23 16 2nd Chunk x8004 MSPL 31 24 x8005 MSPL 23 16 x8006 MSPR 31 24 x8007 MSPR 23 16 3rd Chunk x8008 MSPL 31 24 x8009 MSPL 23 16 x800a MSPR 31 24 x800b MSPR 23 16 4th Chunk x8...

Page 218: ... opposite edge The SPI module can support CPHA 0 and CPHA 1 Motorola SPI transfers as well as generic 3 wire interfaces that require bit transfers that are not an integer number of bytes In DMA modes buffers containing read and write data exist in SDRAM and are accessed via the DMA Engine The size of the buffer is user configurable The SPI module provides the following functionality Motorola SPI s...

Page 219: ...in a cycle can have 1 8 bits DMA Engine Registers for two channels TX and RX the SPI uses the DMA Engine to facilitate data transfer to and from SDRAM 15 2 1 SPI Interface Signals The SPI module is designed to be a SPI master mode device compatible with the Motorola SPI specification In addition it is intended to be a generic 3 wire interface for other 3 wire devices The SPI interface consists of ...

Page 220: ... Byte Timing Relationship 1 SIO_SPI_CS asserts Chip select signal asserts in preparation for data transfer The CSDL field in the SPI_CONFIG register allows adjustment of the setup and hold times of the SIO_SPI_CS n signals about SIO_SPI_CLK CSDL is the number of half SIO_SPI_CLK cycles between SIO_SPI_CS assertion and SIO_SPI_CLK ungating 2 First Bit of Data Transfer Data simultaneously gets shift...

Page 221: ...register 5 SIO_SPI_CS de asserts Chip select signal deasserts data transfer is terminated The CSDL field again determines the number of 1 2 SIO_SPI_CLK cycles between SIO_SPI_CS negation and SIO_SPI_CLK gating 15 2 3 SPI Clocking The SPI module is synchronous to the system clock sysclk and all flops in the module are clocked by this system clock The module uses an internal Clock Enable to generate...

Page 222: ...o polling is necessary as the DMA Engine automatically takes care of reading and writing the SPI_TEMP register when needed 15 2 5 SPI Programming Examples Typical SPI programming sequences for both DMA and non DMA operation are listed below For this example assume a transfer of 16 bytes out and a receive of 16 bytes in over the SPI pins For DMA assume that TX data comes from an allocated SDRAM buf...

Page 223: ...es of dummy data are needed for the ENAB bit in the SPI_CONTROL to deassert when the SPI cycle has completed b Set the TX and RX address pointers as follows TX_addrptr1 0x8004 TX_addrptr2 0x8018 RX_addrptr1 0x9000 RX_addrptr2 0x9010 The RX data region does not need the eight extra bytes of dummy data c Set the RX_control register to 0xd d Set the TX_control register to 0xd Note If the number of by...

Page 224: ...date the SPI_TEMP register with new data and thus clear the HAEN bit BSIZ 10 2 2 times These two extra 32 bit writes are the equivalent of the eight dummy data bytes described in step 3a and must be done before ENAB goes low and the spi_cycle_done interrupt signals If DMA mode is used these updates are handled automatically by the DMA engine and no polling needs to be done For a 16 byte example in...

Page 225: ...ond the ones described above such as generic 3 wire interfaces for example Write only N bits to a device by using the SPI_BITGRAN register Sony SPI interface by setting the LSBF bit in the SPI_CONFIG register Motorola CPHA 0 mode by using the IBBK CSBK and CKBK inter byte blanking fields in the SPI_CONFIG register General Instruments SPI interface by using inter byte blanking and setting the GIMD ...

Page 226: ...annels must always be programmed no true unidirectional transfer The TX size must equal the RX size plus eight bytes l The reason for these requirements is that in a host polled mode transfer the SPI_TEMP register is both written and read with data in a ping pong fashion First SPI_TEMP is written as its bits are shifted out on the pins input data bits are shifted in Once the entire word has been s...

Page 227: ...aster sends out Slave Address MSB first on SIO_SDA Data on SIO_SDA must be stable when SIO_SCL is HIGH only when SIO_SCL is LOW can SIO_SDA change 3 Read Write Bit This bit determines direction of the data transfer If SIO_SDA is HIGH then the master will read from the slave master receiver slave transmitter If SIO_SDA is LOW then the master will write to the slave master transmitter slave receiver...

Page 228: ...re 15 8 shows the composition of the basic UART data frame one start bit eight data bits one stop bit Figure 15 8 UART Data Frame 15 4 2 Baud Rate Generator The baud rate generator implements two 8 bit registers called Divisor Latch Registers DLM and DLL that can be write only accessed by the internal SPARC processor or the external host processor The processor can load 16 bit data into DLM and DL...

Page 229: ...sets from the module base address The module base address of all SIO registers is 0xBE0000 The module base address itself is an offset from the Control Space base address within the 16MB register address space selected by the host as explained in the Product Overview General Description Memory Mapping section of this manual Therefore the physical address of a specific register is the sum of the Co...

Page 230: ...g cycle the appropriate bit in SIO_IRQ_STATUS is set again This indicates that a new interrupt is now pending when it really is not The SIO Top Level DMA Interrupt Status Register SIO_DMA_IRQ stores the bits of the SIO DMA Engine Interrupt Status Register INTR_STATUS_ADDR It is this register INTR_STATUS_ADDR which actually stores the interrupt output pins of all of the various SIO DMA channels In ...

Page 231: ...SIO DMA Engine Interrupt Status register CH_MASK Channel Interrupt Mask 11 1 Each DMA channel has one mask bit associated with it as shown below that is bits in the INTR_MASK_ADDR register correspond to similarly named bits in the INTR_STATUS_ADDR register 1 Any interrupts of type 1 or 2 that occur are recorded in the channel s bits in the SIO DMA Engine Interrupt Sta tus register 0 The channel s ...

Page 232: ...d location as the register is written Any bit positions that contain a 0 during register writes remain unchanged This bit always reads back as 0 SIO DMA Engine Interrupt Status Register INTR_STATUS_ADDR Offset 0xBF0104 Read Write Default 0x0000 0000 Each DMA channel has 2 bits one for each of the possible interrupts ch_intr1 or ch_intr2 for that DMA channel CH_INTR1 2 Channel Interrupt 1 2 22 1 Ea...

Page 233: ...s 20 R1R1 IR1 Receive Interrupt 1 Status 19 R1T2 IR1 Transmit Interrupt 2 Status 18 R1T1 IR1 Transmit Interrupt 1 Status 17 U2R2 UART2 Receive Interrupt 2 Status 16 U2R1 UART2 Receive Interrupt 1 Status 15 U2T2 UART2 Transmit Interrupt 2 Status 14 U2T1 UART2 Transmit Interrupt 1 Status 13 U1R2 UART1 Receive Interrupt 2 Status 12 U1R1 UART1 Receive Interrupt 1 Status 11 U1T2 UART1 Transmit Interrup...

Page 234: ...ng a transaction with SDRAM P2 P1 P0 Priority Mode 10 8 These bits set the priority mode as shown in Table 15 4 Programmable Priority This setting P2 P0 001 is used to alter the priority of the DMA channels in case a particular target channel requires the highest priority whatever the arbitration scheme that is selected The programming of these bits overrides the default behavior The highest prior...

Page 235: ...blaster 2 IR2_TX has the lowest Table 15 5 explains the channel numbers This can be changed to programmable priority fixed priority or rotating priority TGT_ID Target Module ID 7 0 Legal values for the target ID are shown in Table 15 5 SIO Top Level Module Interrupt Status Register SIO_IRQ_STATUS Offset 0xBF0140 Read Write Default 0x0000 0000 This register depending on the value of the correspondi...

Page 236: ... Note Before clearing an Interrupt Status bit software must resolve the corresponding module s interrupt as described in the particular module s section in this chapter Note that the procedure to resolve the interrupt varies from module to module Refer to Section 15 5 1 Interrupt Hierarchy page 15 20 for more details IR2T IR2 Transmit Interrupt Status 8 IR1R IR1 Receive Interrupt Status 7 IR1T IR1...

Page 237: ...arget module 0 The corresponding interrupt is ignored IR2T IR2 Transmit Interrupt Enable 8 IR1R IR1 Receive Interrupt Enable 7 IR1T IR1 Transmit Interrupt Enable 6 UA2I UART2 Interrupt Enable 5 UA1I UART1 Interrupt Enable 4 IDCI IDC Interrupt Enable 3 SPIC SPI Cycle Done Interrupt Enable 2 ACT Action Bit 0 This bit is an action bit The value of this bit is written to any selected bits during regis...

Page 238: ...egister Modules must be explicitly reset to 1 then released to 0 before use Reset 5 0 Each of the bits shown below is tied to the reset pin of the corresponding module 1 Reset IR2R IR2 Reset 5 IR1R IR1 Reset 4 UA2R UART2 Reset 3 UA1R UART1 Reset 2 IDCR IDC Reset 1 SPIR SPI Reset 0 SIO Top Level DMA Interrupt Status Register SIO_DMA_IRQ Offset 0xBF014C Read Write Default 0x0000 0000 31 16 RSVD 15 6...

Page 239: ...mine which module DMA channel is the source of the interrupt and act accordingly Since the bits in this register are simply recorded versions of the OR ing of the DMA channel interrupt bits that is bits 2 1 of INTR_STATUS_ADDR OR ed and recorded in bit 1 bits 4 3 of INTR_STATUS_ADDR OR ed and recorded in bit 2 etc the user must service the interrupt at the DMA channel level before explicitly clear...

Page 240: ...tion 15 5 1 Interrupt Hierarchy page 15 20 for more details R2DT IR2 DMA Transmit Interrupt Status 11 R1DR IR1 DMA Receive Interrupt Status 10 R1DT IR1 DMA Transmit Interrupt Status 9 U2DR UART2 DMA Receive Interrupt Status 8 U2DT UART2 DMA Transmit Interrupt Status 7 U1DR UART1 DMA Receive Interrupt Status 6 U1DT UART1 DMA Transmit Interrupt Status 5 SPDR SPI DMA Receive Interrupt Status 2 SPDT S...

Page 241: ...egister R2DT IR2 DMA Transmit Interrupt Mask 11 R1DR IR1 DMA Receive Interrupt Mask 10 R1DT IR1 DMA Transmit Interrupt Mask 9 U2DR UART2 DMA Receive Interrupt Mask 8 U2DT UART2 DMA Transmit Interrupt Mask 7 U1DR UART1 DMA Receive Interrupt Mask 6 U1DT UART1 DMA Transmit Interrupt Mask 5 SPDR SPI DMA Receive Interrupt Mask 2 SPDT SPI DMA Transmit Interrupt Mask 1 ACT Action Bit 0 This bit is an act...

Page 242: ...ge in Slave Receiver Mode 29 1 A Nack is generated after the current byte is received in slave receiver mode 0 A stop start or repeat start condition is detected This bit reads back as 0 VD Byte2Rd field has valid data 28 1 Transfer data from bits 27 23 to the internal state machine This bit clears itself and reads back as 0 Byte2Rd of Bytes to read when Master Receiver 27 24 This field tells the ...

Page 243: ...d This bit is used only in master mode FR Flush RX Data Fifo 21 1 Reset the receive data FIFO This bit clears itself and reads back as 0 FT Flush TX Data Fifo 20 1 Reset the transmit data FIFO This bit clears itself and reads back as 0 IE Interrupt Enable 19 1 Interrupts will be generated RS Repeat Start 18 1 Generate a Repeat Start at the end of the current master mode operation all bytes transmi...

Page 244: ...3 22 21 20 19 18 17 16 Reserved LA SN TxE SD RS SAd MI SI NAK AK RxR Gen CSO 15 0 Reserved Table 15 6 Status Register Events Mode Condition Master Transmitter Tx FIFO is empty and the LB bit of IDC_Control1 is clear Tx FIFO is empty the LB bit of IDC_Control1 is set and the STOP condition has been generated No acknowledge was received after transmitting the slave address on the bus Master Receiver...

Page 245: ...Repeat Start 24 1 A Repeat Start was detected with the IDC device address active or a Repeat Start was generated SAd Slave Address 23 1 The slave state machine detected a start condition and the address is the IDC device address Slave Transmitter An address is recognized on the bus that matches the value in IIDC_Status1 Tx FIFO is empty The STOP condition has been detected The Repeat Start conditi...

Page 246: ...sent out data when the IDC was in master slave transmitter mode AK Acknowledge 19 1 The addressed slave returned an acknowledge dur ing the address phase RxR Rx Data Ready 18 1 The receive FIFO is not empty Gen General Call 17 1 The slave detected a general call address CSO Current Slave Operation 16 Meaningful in slave mode only 1 External master is reading DMN 8600 0 External master is writing t...

Page 247: ...his location reads data from the 8 byte RX FIFO Data is placed in the RX FIFO when the IDC device is either the master of a valid read or the slave of a valid write Caution Do not read more bytes from this register than the number indicated in the RxCnt field of the IDC FIFO Fullness register Attempting to read more bytes than are available will corrupt the RxCnt value requiring a software reset 3...

Page 248: ...C_TX_DATA Offset 0xBE0094 Write Only Default 0x0000 0000 TxData Transmit Data 23 16 Writing to this location writes data to the 8 byte transmit FIFO The data in the transmit FIFO is transmitted over the IDC lines SIO_SDA and SIO_SCL when the IDC device is either the master during a write or the slave during a read This is a write only register Caution In the master transmitter mode the transmit FI...

Page 249: ...also affected by the amount of filtering applied by the IDC Receive Filter register Since this filtering internally delays the rising edges of the SIO_SCL line it effectively slows down the bus With filtering employed the IDC clock frequency is on the order of frequency sysclk 4 IDCSCL IDCSAMP 1 IDCRISE 1 IDC FIFO Fullness Register IDC_FIFO_STATUS Offset 0xBE009C Read Only Default 0x0000 0000 Byte...

Page 250: ...d and if either its address or a general call is recognized on the bus an ACK is immediately generated SAN Slave Address NAK 17 This bit is ignored in compatibility mode In other modes 1 The slave address is NACKed 0 The slave address is ACKed Go Hold Go autoclear 16 This bit is ignored in compatibility mode In other modes 1 The SIO_SDA line transmits ACK or NAK according to the value in the SAN b...

Page 251: ... falling transitions until a given number of consecutive high or low states has been sampled IDCFALL IDC Falling Edge 31 28 This field sets the number of consecutive low samples required to pass a falling edge The actual value used is IDCFALL 1 IDCRISE IDC Rising Edge 23 20 This field sets the number of consecutive high samples required to pass a rising edge The actual value used is IDCRISE 1 Note...

Page 252: ...e DMN 8600 always runs in double buffer mode Single buffer ring buffer mode is not supported MODE Transfer Mode Select 2 This bit must always be set to 1 so that the channel operates in double buffer mode FLUS FIFO Flush 1 This is a self clearing bit for flushing the DMA channel s two internal FIFOs When FLUS is set for transmit channels all data currently in the channel FIFOs is dropped When FLUS...

Page 253: ...e Default 0x0000 0000 FLSTS FIFO Flush Status 19 1 The flushing of a particular DMA channel is complete Software must reset FLSTS by writing 0 FLVLB FIFO B Byte Count 18 10 This field shows the number of bytes currently held in FIFO B FLVLA FIFO A Byte Count 9 1 This field shows the number of bytes currently held in FIFO A CHST DMA Channel Status 0 1 The DMA transfer operation has finished CHST ca...

Page 254: ...X_ADDR_PTR2_ADDR Offset 0xBE00CC Read Write Default 0x0000 0000 ADDR_PTR2 Address Pointer 2 27 0 In double buffer mode this register indicates the End Address for the next SDRAM buffer about to be trans ferred Note The maximum size for each SDRAM buffer transfer is 511 bytes Therefore the difference between ADDR_PTR2 and ADDR_PTR1 should not exceed 511 IDC DMA Transmit Address Pointer 3 Register I...

Page 255: ...ted IDC DMA Transmit Address Pointer 4 Register IDC_TX_ADDR_PTR4_ADDR Offset 0xBE00D4 Read Write Default 0x0FFF FFFF ADDR_PTR4 Address Pointer 4 27 0 In double buffer mode this register is loaded with the contents of ADDR_PTR2 if Go is high and if either of the following is true The DMA channel is idle The previous SDRAM buffer has completed IDC DMA Receive Control Register IDC_RX_CONTROL_REG_ADDR...

Page 256: ...ransmit channels all data currently in the channel FIFOs is dropped When FLUS is set for receive channels all data currently in the channel FIFOs is sent to the SDRAM address indi cated by ADDR_PTR3 Setting FLUS does not terminate a transfer it merely dumps data if transmit or sends whatever data remains in the FIFOs up to the SDRAM if receive CHEN DMA Channel Enable 0 This bit enables disables th...

Page 257: ...ly held in FIFO A CHST DMA Channel Status 0 1 The DMA transfer operation has finished CHST can be cleared by writing 1 to it IDC DMA Receive Address Pointer 1 Register IDC_RX_ADDR_PTR1_ADDR Offset 0xBE00E8 Read Write Default 0x0000 0000 ADDR_PTR1 Address Pointer 1 27 0 In double buffer mode this register indicates the Base Address for the next SDRAM buffer about to be trans ferred Note The maximum...

Page 258: ...R_PTR2 and ADDR_PTR1 should not exceed 511 IDC DMA Receive Address Pointer 3 Register IDC_RX_ADDR_PTR3_ADDR Offset 0xBE00F0 Read Write Default 0x0000 0000 ADDR_PTR3 Address Pointer 3 27 0 This register is updated by hardware during a DMA oper ation For write channels transmit this register indicates the current value of the write pointer in SDRAM For read channels receive it indicates the current ...

Page 259: ...is high and if either of the following is true The DMA channel is idle The previous SDRAM buffer has completed 15 5 4 SIO IR1 IR2 Registers IR1 Transmit Carrier Wave Period Register IR1_CWP IR2 Transmit Carrier Wave Period Register IR2_CWP Offset 0xBF0000 0xBF0080 Read Write Default 0x3FFF0000 CWP Carrier Wave Period 29 16 This register encodes the period of the IR carrier wave in units of sysclk ...

Page 260: ...carrier wave pulse high period is CWPH 12 0 1 IR1 Modulated Signal Period Register IR1_MSPR IR2 Modulated Signal Period Register IR2_MSPR Offset 0xBF0008 0xBF0088 Read Write Default 0x0000 0000 This is one of two registers written to produce an IR output The other one is the IR Modulated Signal Pulse Low IR_MSPL register Since this register contains the enable bit that initiates the transmission i...

Page 261: ...ster is sufficiently large to support the 9 ms pulse required for the start bit in the NEC format IR1 Modulated Signal Pulse Low Register IR1_MSPL IR2 Modulated Signal Pulse Low Register IR2_MSPL Offset 0xBF000C 0xBF008C Read Write Default 0x0000 0000 This register is one of two registers that is written to produce a bit stream output Since the IR1_MSPR contains the enable bit that initiates the t...

Page 262: ... or falling edge of SIO_IRRX depending on the settings of bit 24 in the IR1 Receive Filter Register IR1_RFR S Filter Start Pulse 24 1 The IR receiver is disabled until IRRX is asserted for a period specified by the IR Receive Filter register 0 The IR receiver is always enabled This value is cleared after the reception of a valid start pulse RTC Receive Tick Count 23 16 The tick count register reco...

Page 263: ...R receive signal SIO_IRRX P IR RX Signal Polarity 24 This bit sets the input signal SIO_IRRX polarity 1 SIO_IRRX is active low and RTC reports the time between rising edges of SIO_IRRX while RPH reports the time that IRRX is low 0 SIO_IRRX is active high and RTC reports the time between falling edges of SIO_IRRX while RPH reports the time that SIO_IRRX is high This bit is set to zero on reset Filt...

Page 264: ...3 IR1 Receive Pulse High Tick Count Register IR1_RPH Offset 0xBF001C Read Write Default 0x0000 0000 RHTC Receive Pulse High Tick Count 23 16 This register contains the high pulse width for the previ ously received input pulse This register is loaded after each deassertion of the SIO_IRRX input Note that the default value of each tick is 7032 cycles The tick period can be modified by programming th...

Page 265: ...aded It is also cleared on reset MODE Transfer Mode Select 2 This bit must always be set to 1 so that the channel operates in double buffer mode FLUS FIFO Flush 1 This is a self clearing bit for flushing the DMA channel s two internal FIFOs 1 For transmit channels all data currently in the chan nel FIFOs is dropped 1 For receive channels all data currently in the channel FIFOs is sent to the SDRAM...

Page 266: ...t FLSTS by writing 0 FLVLB FIFO B Byte Count 18 10 This field shows the number of bytes currently held in FIFO B FLVLA FIFO A Byte Count 9 1 This field shows the number of bytes currently held in FIFO A CHST DMA Channel Status 0 1 The DMA transfer operation has finished CHST can be cleared by writing 1 to it IR1 DMA Transmit Address Pointer1 Register IR_TX_ADDR_PTR1_ADDR IR2 DMA Transmit Address P...

Page 267: ...R2 DMA Transmit Address Pointer2 Register IR2_TX_ADDR_PTR2_ADDR Offset 0xBF004C 0xBF00CC Read Write Default 0x0000 0000 ADDR_PTR2 Address Pointer 2 27 0 In double buffer mode this register indicates the End Address for the next SDRAM buffer about to be trans ferred Note The maximum size for each SDRAM buffer transfer is 511 bytes Therefore the difference between ADDR_PTR2 and ADDR_PTR1 should not ...

Page 268: ...ter is loaded with the contents of ADDR_PTR1 if Go is high and if either of the following is true The DMA channel is idle The previous SDRAM buffer has completed IR1 DMA Transmit Address Pointer4 Register IR_TX_ADDR_PTR4_ADDR IR2 DMA Transmit Address Pointer4 Register IR2_TX_ADDR_PTR4_ADDR Offset 0xBF0054 0xBF00D4 Read Write Default 0x0FFF FFFF ADDR_PTR4 Address Pointer 4 27 0 In double buffer mod...

Page 269: ...ode Single buffer ring buffer mode is not supported Go is set by software after the address range for the next buffer is programmed ADDR_PTR1 ADDR_PTR2 Go is cleared by the hardware after these next values are loaded It is also cleared on reset MODE Transfer Mode Select 2 This bit must always be set to 1 so that the channel operates in double buffer mode FLUS FIFO Flush 1 This is a self clearing b...

Page 270: ...cleared once the DMA operation has finished On reset CHEN is 0 IR1 DMA Receive Status Register IR_RX_STATUS_REG_ADDR Offset 0xBF0064 Read Write Default 0x0000 0000 FLSTS FIFO Flush Status 19 1 Flushing of a particular DMA channel is complete Software must reset FLSTS by writing 0 FLVLB FIFO B Byte Count 18 10 This field shows the number of bytes currently held in FIFO B FLVLA FIFO A Byte Count 9 1...

Page 271: ... each SDRAM buffer transfer is 511 bytes Therefore the difference between ADDR_PTR2 and ADDR_PTR1 should not exceed 511 IR1 DMA Receive Address Pointer2 Register IR_RX_ADDR_PTR2_ADDR Offset 0xBF006C Read Write Default 0x0000 0000 ADDR_PTR2 Address Pointer 2 27 0 In double buffer mode this register indicates the End Address for the next SDRAM Buffer about to be trans ferred Note The maximum size fo...

Page 272: ... the current value of the read pointer In double buffer mode this register is loaded with the contents of ADDR_PTR1 if Go is high and if either of the following is true The DMA channel is idle The previous SDRAM buffer has completed IR1 DMA Receive Address Pointer4 Register IR_RX_ADDR_PTR4_ADDR Offset 0xBF0074 Read Write Default 0x0FFF FFFF ADDR_PTR4 Address Pointer 4 27 0 In double buffer mode th...

Page 273: ... in this mode all SPI signal lines are mapped to bytes in the SPI_TEMP register For each byte time the value of byte n in the SPI_TEMP register is held static and the bits are mapped to the SPI signal lines as shown in Table 15 7 31 30 24 23 22 21 18 17 16 BBMD SPED 6 0 HUEN OIN CSPL 3 0 CPOL CPHA 15 14 13 10 9 8 7 6 4 3 0 ODW ODR IBBK 3 0 CSBK IBBM LSBF CSDL 2 0 CSSL 3 0 Table 15 7 Bit bang Mode ...

Page 274: ...clk 2 progdiv 2 where progdiv HDIV SPED That is progdiv is the concatenation of HDIV bits in the SPI Clock Divider register with the SPED bits the SPI Configuration register HUEN Host Update Enable 23 1 Set the update mode to either single word mode or host polled mode Values are given in Table 15 8 Table 15 8 SPI Transfer Modes HUEN ODW ODR Description 0 0 0 Single word mode The SPI interface out...

Page 275: ...rom the value of SIO_SPI_CLK when the SPI interface is idle 0 The SIO_SPI_CLK line on the first half of the first bit period of a SPI transaction is the same as the value of SIO_SPI_CLK when the SPI interface is idle ODW 15 This bit must always be written as 0 ODR 14 This bit must always be written as 0 IBBK Inter Byte Blanking Period 13 10 This is the inter byte blanking period in bits where depe...

Page 276: ...d out first and each read byte in the SPI_SHIFT register is swapped before writing it to the SPI_TEMP register Since the swapping occurs between the SPI_SHIFT reg ister and the data registers software must shift bits for bytes in the SPI_SHIFT register 0 The most significant bit of each write byte is shifted out first CSDL 2 0 SPI Chip Select Delay 6 4 These bits allow adjustment of the setup and ...

Page 277: ...ng is shown in Table 15 9 When the SPI cycle is idle all four chip select lines are in the negated state set by CSPL Note Additional selects can be decoded through external logic if required SPI Control Register SPI_CONTROL Offset 0xBE0004 Read Write Default 0x0000 0000 HAEN Host Access Enable 1 1 Host access of SPI_TEMP is enabled HAEN is set when the SPI_TEMP register is loaded with the contents...

Page 278: ...sfer completes This bit can be polled by software to check for cycle com pletion Note Reset interrupts the current cycle and clears this bit SPI DMA Size Register SPI_DMASIZE Offset 0xBE0010 Read Write Default 0x0000 0000 BSIZ SPI Data Transfer 10 0 This field defines the size of the data block to be trans ferred by the SPI interface over the pins In host polled mode the host or SPARC processor mu...

Page 279: ... pong fashion first write then read then write If the LSBF bit is set then for each byte the bits are sent out LSB first and the bit ordering of each byte is reversed from the order in which the bits were received on the SIO_SPI_MISO pin SPI Shift Register SPI_SHIFT Offset 0xBE0018 Read Write Default 0x0000 0000 SREG Shift Register 31 0 This is a shift register for the SIO_SPI_MOSI and SIO_SPI_MIS...

Page 280: ...Offset 0x 0xBE0020 Read Write Default 0x0000 0000 BCNT SPI Bit Granularity 2 0 BCNT together with the BSIZ field in the SPI_SIZE reg ister allows the SPI interface to have bit granularity on the last 32 bit word in a SPI cycle to be transferred After SPI_TEMP is written with the final word of data any where from 8 to 32 of these bits can be sent out on the pins Sending out less than 8 bits is not ...

Page 281: ...ber of Bits Sent Depending on Programmed Values of BSIZ and BCNT BSIZ BCNT Bits Sent BSIZ BCNT Bits Sent 0 0 8 2 0 24 0 1 N A 2 1 17 0 2 N A 2 2 18 0 3 N A 2 3 19 0 4 N A 2 4 20 0 5 N A 2 5 21 0 6 N A 2 6 22 0 7 N A 2 7 23 1 0 16 1 1 9 1 2 10 4 0 40 32 8 1 3 11 4 5 37 32 5 1 4 12 14 0 120 32 32 32 24 1 5 13 14 7 119 32 32 32 23 1 6 14 17 0 144 32 32 32 32 16 1 7 15 17 6 142 32 32 32 32 14 31 16 RS...

Page 282: ...ntrol when ADDR_PTR1 and ADDR_PTR2 for a particular DMA channel are loaded into the current buffer address registers ADDR_PTR3 and ADDR_PTR4 in double buffer mode operation Note The maximum size for each SDRAM buffer transfer is 511 bytes Therefore the difference between ADDR_PTR2 and ADDR_PTR1 should not exceed 511 Note DoMiNo always runs in double buffer mode Single buffer ring buffer mode is no...

Page 283: ...ables disables the DMA channel If CHEN is cleared during a DMA operation DMA is paused Set CHEN again to resume the DMA operation All state information is preserved when DMA is paused and the DMA operation continues from where it left off CHEN is controlled by software It must be cleared once the DMA operation has finished On reset CHEN is 0 SPI DMA Transmit Status Register SPI_TX_STATUS_REG_ADDR ...

Page 284: ...out to be trans ferred Note The maximum size for each SDRAM buffer transfer is 511 bytes Therefore the difference between ADDR_PTR2 and ADDR_PTR1 should not exceed 511 SPI DMA Transmit Address Pointer2 Register SPI_TX_ADDR_PTR2_ADDR Offset 0xBE004C Read Write Default 0x0000 0000 ADDR_PTR2 Address Pointer 2 27 0 In double buffer mode this register indicates the End Address for the next SDRAM buffer...

Page 285: ...cates the current value of the read pointer In double buffer mode this register is loaded with the contents of ADDR_PTR1 if Go is high and if either of the following is true The DMA channel is idle The previous SDRAM buffer has completed SPI DMA Transmit Address Pointer4 Register SPI_TX_ADDR_PTR4_ADDR Offset 0xBE0054 Read Write Default 0x0FFF FFFF ADDR_PTR4 Address Pointer 4 27 0 In double buffer ...

Page 286: ...ingle buffer ring buffer mode is not supported Go is set by software after the address range for the next buffer is programmed ADDR_PTR1 ADDR_PTR2 Go is cleared by the hardware after these next values are loaded It is also cleared on reset MODE Transfer Mode Select 2 This bit must always be set to 1 so that the channel operates in double buffer mode FLUS FIFO Flush 1 This is a self clearing bit fo...

Page 287: ... be cleared once the DMA operation has finished On reset CHEN is 0 SPI DMA Receive Status Register SPI_RX_STATUS_REG_ADDR Offset 0xBE0064 Read Write Default 0x0000 0000 FLSTS FIFO Flush Status 19 1 Flushing of a particular DMA channel is complete Software must reset FLSTS by writing 0 FLVLB FIFO B Byte Count 18 10 This field shows the number of bytes currently held in FIFO B FLVLA FIFO A Byte Coun...

Page 288: ... SDRAM buffer transfer is 511 bytes Therefore the difference between ADDR_PTR2 and ADDR_PTR1 should not exceed 511 SPI DMA Receive Address Pointer2 Register SPI_RX_ADDR_PTR2_ADDR Offset 0xBE006C Read Write Default 0x0000 0000 ADDR_PTR2 Address Pointer 2 27 0 In double buffer mode this register indicates the End Address for the next SDRAM buffer about to be trans ferred Note The maximum size for ea...

Page 289: ...cates the current value of the read pointer In double buffer mode this register is loaded with the contents of ADDR_PTR1 if Go is high and if either of the following is true The DMA channel is idle The previous SDRAM buffer has completed SPI DMA Receive Address Pointer4 Register SPI_RX_ADDR_PTR4_ADDR Offset 0xBE0074 Read Write Default 0x0FF FFFFF ADDR_PTR4 Address Pointer 4 27 0 In double buffer m...

Page 290: ...determines which register is physically written or read as shown below Write UART _DLL when DLAB 1 Write UART _THR when DLAB 0 Read UART _RBR when DLAB 0 In any case each of these three registers is always accessed via the same software name UART1_RBR0_THR0_DLL1 or UART2_RBR0_THR0_DLL1 UART1 UART2 Divisor Latch LSB Register DLL Offset 0xBE0100 0xBE0180 Write only Default 0x0000 0000 DLSB Divisor L...

Page 291: ...ferred to the Transmit Shift Register at an appro priate time and is transmitted on the SOUT pin After module reset the Transmit Holding Register is empty so the THRE bit in the Line Status Register is set This causes an interrupt to the SPARC processor if the interrupts of the UART are enabled The SPARC proces sor can reset this interrupt by either loading data into the Transmit Holding Register ...

Page 292: ...t This can cause an interrupt to the SPARC pro cessor if interrupts are enabled The DR bit is reset only when the SPARC processor reads the Receive Buffer Register or when all the data from the receive FIFO has been drained in FIFO mode UART1 Interrupt Enable Register Divisor Latch MSB Register UART1_IER0_DLM1 UART2 Interrupt Enable Register Divisor Latch MSB Register UART2_IER0_DLM1 In effect two...

Page 293: ...st significant bits DMSB and DLL holds the eight least significant bits DLSB to obtain an output nBD OUT from the baud rate generator that is 16 times the desired baud rate Refer to Section 15 4 2 Baud Rate Generator page 15 18 for more information on generating a desired baud rate from a given system clock UART1 UART2 Interrupt Enable Register IER Note The value of the DLAB bit in the UARTn Line ...

Page 294: ...odem status interrupt source to activate the interrupt signal of the UART module This source is the DCTS bit in the Modem Status Register RLSE Receiver Line Status Interrupt Enable 26 1 Enable the receiver line status interrupt sources to activate the interrupt signal of the UART module These sources are the OE PE FE and BI bits in the Line Sta tus Register THREE Transmit Holding Register Empty In...

Page 295: ...gether with the DLL to generate the NBDOUT from the input clock UART1 Interrupt Identification FIFO Control Register UART1_IIR_FCR UART2 Interrupt Identification FIFO Control Register UART2_IIR_FCR In effect two registers share the offset address 0x108 UART1_IIR and UART1_FCR Similarly two registers share the offset address 0x188 UART2_IIR and UART2_FCR The read or write operation determines which...

Page 296: ...FO 31 30 A value of 11 in this field indicates the FIFO mode of operation Otherwise these two bits are set to 0 P3 P2 P1 P0Priority 27 24 These bits give the interrupt type and priority as shown in Table 15 11 31 30 29 28 27 26 25 24 23 16 FIFO 0 0 P3 P2 P1 P0 RSVD 15 0 RSVD Table 15 11 Interrupt Identification Register Details P3 P2 P1 P0 Priority Level Interrupt Type 0 0 0 1 None 0 1 1 0 Highest...

Page 297: ...e to feed drain the UARTs with data FCR 2 Clear Transmit FIFO 26 1 Clear all bytes in the transmit FIFO and reset its counter to 0 The shift register is not cleared The 1 that is written to this bit is self clearing FCR 1 Clear Receive FIFO 25 1 Clear all bytes in the receive FIFO and resets its counter to 0 The shift register is not cleared The 1 that is written to this bit is self clearing FCR 0...

Page 298: ...O mode is enabled UART1 Line Control Register UART1_LCR UART2 Line Control Register UART2_LCR Offset 0xBE010C 0xBE018C Read Write Default 0x0000 0000 The UART is configured to operate as follows Transmit 5 bits character and 1 stop bit Parity disabled Odd parity selected SP is 0 SB is disabled DLAB is 0 which means that the first access to the DLL THR RBR and the DLM IER registers will not be to b...

Page 299: ...on and transmission of parity bit in the transmitter and receiver and the checking of parity bits in the receiver block of the UART STB Stop Bits 26 This bit along with WLS 1 0 sets the number of bits to be transmitted received per character and the number of stop bits to be transmitted per character The receiver checks for the first stop bit only Details are shown in Table 15 13 WLS 1 0 Word Leng...

Page 300: ...ulating the modem After module reset this register is set to no loopback and all modem control output pins are high RTS Request To Send 25 If hardware flow control is enabled then the SIO_UART _RTS pin and this bit acts as a function of the receive FIFO s fullness the software programmed value is ignored The output RTS strobe is deasserted pin high bit low if the receive FIFO has only two byte slo...

Page 301: ... the Line Status Register is read and there are no subsequent errors in the FIFO TEMT Transmitter Empty 30 1 Both the Transmitter Holding Register and the Trans mitter Shift Register are empty transmitter idle condi tion THRE Transmit Holding Register Empty 29 1 The UART is ready to accept a new character for transmission This bit causes the UART to issue an inter rupt to the host processor when t...

Page 302: ... FIFO The UART will try to resynchronize after the fram ing error To do this it assumes that the framing error was due to the next start bit so it samples this start bit twice and then it takes in the data PE Parity Error 26 1 The received character does not have correct parity The PE bit is set upon detection of parity error and is reset when the host processor reads the contents of the Line Stat...

Page 303: ...red to the receive FIFO It is reset after reading all the bytes from the receive FIFO UART1 Modem Status Register UART1_MSR UART2 Modem Status Register UART2_MSR Offset 0xBE0118 0xBE0198 Read Write Default 0x0000 0000 CTS Clear To Send 28 This bit reflects the state of the CTS input of the UART The CTS bit is the complement of the value coming into the SIO_UART _CTS pin 1 CTS pin is active low 0 C...

Page 304: ... the UART operation in any way It can be used to hold data temporarily UART1 External Clock Prescaler Register UART1_PRESCALER UART2 External Clock Prescaler Register UART2_PRESCALER Offset 0xBE0120 0xBE01A0 Read Write Default 0x0A00 0000 DIV Clock Divider 31 24 This register can alter the frequency of the external input clock which is fed back into the UART Note These registers are known as UART1...

Page 305: ...byte if CTS is high then do not send data out on the pins Race conditions result in data going out RX The output RTS strobe is deasserted if the receive FIFO is at a level of 2 bytes from full and is reasserted when it is 3 bytes from full The software programmed value in the Modem Control Register is ignored and the register bit reflects the output on the SIO_UART _RTS pin 0 Hardware flow control...

Page 306: ...It is also cleared on reset MODE Transfer Mode Select 2 This bit must always be set to 1 so that the channel operates in double buffer mode FLUS FIFO Flush 1 This is a self clearing bit for flushing the DMA channel s two internal FIFOs 1 For transmit channels all data currently in the chan nel FIFOs is dropped 1 For receive channels all data currently in the channel FIFOs is sent to the SDRAM addr...

Page 307: ...S by writing 0 FLVLB FIFO B Byte Count 18 10 This field shows the number of bytes currently held in FIFO B FLVLA FIFO A Byte Count 9 1 This field shows the number of bytes currently held in FIFO A CHST DMA Channel Status 0 1 The DMA transfer operation has finished CHST can be cleared by writing 1 to it UART1 DMA Transmit Address Pointer1 Register UART1_TX_ADDR_PTR1_ADDR UART2 DMA Transmit Address ...

Page 308: ...Transmit Address Pointer2 Register UART2_TX_ADDR_PTR2_ADDR Offset 0xBE014C 0xBE01CC Read Write Default 0x0000 0000 ADDR_PTR2 Address Pointer 2 27 0 In double buffer mode this register indicates the End Address for the next SDRAM Buffer about to be trans ferred Note The maximum size for each SDRAM buffer transfer is 511 bytes Therefore the difference between ADDR_PTR2 and ADDR_PTR1 should not excee...

Page 309: ...ter is loaded with the contents of ADDR_PTR1 if Go is high and if either of the following is true The DMA channel is idle The previous SDRAM buffer has completed UART1 DMA Transmit Address Pointer4 Register UART1_TX_ADDR_PTR4_ADDR UART2 DMA Transmit Address Pointer4 Register UART2_TX_ADDR_PTR4_ADDR Offset 0xBE0154 0xBE01D4 Read Write Default 0x0FFF FFFF ADDR_PTR4 Address Pointer 4 27 0 In double b...

Page 310: ...e is not supported Go is set by software after the address range for the next buffer is programmed ADDR_PTR1 ADDR_PTR2 Go is cleared by the hardware after these next values are loaded It is also cleared on reset MODE Transfer Mode Select 2 This bit must always be set to 1 so that the channel operates in double buffer mode FLUS FIFO Flush 1 This is a self clearing bit for flushing the DMA channel s...

Page 311: ...has finished On reset CHEN is 0 UART1 DMA Receive Status Register UART1_RX_STATUS_REG_ADDR UART2 DMA Receive Status Register UART2_RX_STATUS_REG_ADDR Offset 0xBE0164 0xBE01E4 Read Write Default 0x0000 0000 FLSTS FIFO Flush Status 19 1 Flushing of a particular DMA channel is complete Software must reset FLSTS by writing 0 FLVLB FIFO B Byte Count 18 10 This field shows the number of bytes currently ...

Page 312: ... SDRAM buffer transfer is 511 bytes Therefore the difference between ADDR_PTR2 and ADDR_PTR1 should not exceed 511 UART1 DMA Receive Address Pointer2 Register UART1_RX_ADDR_PTR2_ADDR UART2 DMA Receive Address Pointer2 Register UART2_RX_ADDR_PTR2_ADDR Offset 0xBE016C 0xBE01EC Read Write Default 0x0000 0000 ADDR_PTR2 Address Pointer 2 27 0 In double buffer mode this register indicates the End Addres...

Page 313: ...channels transmit this register indicates the current value of the write pointer in SDRAM For read channels receive it indicates the current value of the read pointer In double buffer mode this register is loaded with the contents of ADDR_PTR1 if Go is high and if either of the following is true The DMA channel is idle The previous SDRAM buffer has completed UART1 DMA Receive Address Pointer4 UART...

Page 314: ... Go is high and if either of the following is true The DMA channel is idle The previous SDRAM buffer has completed 15 5 7 Reserved Registers SIO UART2 UART2 Modem Control Register UART2_MCR Offset 0xBE0190 Read Write Default 0x0000 0000 UART2 Modem Status Register UART2_MSR Offset 0xBE0198 Read Write Default 0x0000 0000 UART2 Hardware Flow Control Register UART2_HW_FLOW_CTRL Offset 0xBE01A4 Read W...

Page 315: ...stal oscillator or externally generated 13 5 or 27 MHz system clocks are used as the reference frequency for the PLLs The 13 5 MHz reference frequency is also used as the clock for the PTS time stamp counters in the AV I O and BIO units The DMN 8600 has a full power down mode which shuts down all PLLs and logic operating from the internally generated clocks Power down mode is exited by hardware re...

Page 316: ...O_MCLKI VI_CLK 0 VI_CLK 1 VO_CLK Main PLL Clock Control Register Xtal Osc DIV 2 SYRISC_CLK Note AND gate unconnected inputs are from power management register VSPARC_CLK SDRAMCTL_CLK VDSP_CLK ME_CLK SIO_CLK PTS13_5MHZ BIOXPORT_CLK BIOSTORAGE_CLK BIOLCC_CLK RESERVED HOSTMAST_CLK HOSTSLAVE_CLK CLKCTRL_CLK VIOCC_CLK VIN1Clock to VIO VIN2Clock to VIO VOUTClock to VIO MIClock to AIO AIO_CLK MOClock to ...

Page 317: ... the master or CBus address space Software should poll this register until this bit reads as one to be sure that the sdram is actually stopped When software writes zero to this bit and the bit is set the sdrams are taken out of standby refresh mode Software should poll this register until this bit reads as zero to be sure that the sdram is actually enabled The SDRAMs should not be enabled until th...

Page 318: ... from its nominal 13 5 MHz operating point in sign magnitude format in the range of 15 to 15 The maximum positive and negative offsets correspond to a frequency adjustment of 100 ppm The frequency adjustment can only be applied when a 13 5 MHz crystal is used This field is reset to 01111 For proper operation of the crystal oscillator software should not change the value of Adj 4 0 by more than one...

Page 319: ...it is assumed to be 13 5 MHz The 13 5 MHz clock is divided by 150 before being accumulated in the video PTS counter register This bit is reset to one The internal clock operating frequency is determined by N and P as follows SysclkPLL N is determined by the table below After reset N is set to 4 and P is set to 1 Software must change N and P to correct values after reset Changing the internal clock...

Page 320: ...occur N 4 2 See above This field is reset to 0x4 P 1 See above Default value equals 1 resetDLL 0 See above Default value equals 0 Video Output Clock Control Register Memory Space Address 0xC2000C VinSrc27 9 If set the Video Input 1 Clock pin is divided by two before being applied to the PLLs This bit should be set if the external Video Input 1 Clock pin is 27 MHz otherwise it is assumed to be 13 5...

Page 321: ...an operating frequency is determined by N and P as follows VidOutPLL N is determined by the table below After reset N and P are set to 0 N 6 4 See above This field is reset to 0 P 3 2 See above This field is reset to 0 VideoOut PLL Src Value PLL Source Clock Application 0 If Osync clear Clk pin else Video Input 1 Clock pin Internally generated video output timing 1 Video Input 1 Clock pin Video Ou...

Page 322: ...is used as supplied on the AI_MCLKI pin In either case the internally generated master input audio clock is output on the AI_MCLKO pin At reset this bit set if the PLL_BYPASS pin is zero otherwise it is reset The internal audio input master clock operating frequency is determined by N and P as follows N is interpreted as a 3 24 bit fractional number In DoMiNo N values are restricted so that 13 5 M...

Page 323: ...g If clear then an external master output clock is used as supplied on the MOclockI pin In either case the internally generated master audio clock is output on the MOclockO pin At reset this bit set if the PLL_BYPASS pin is zero otherwise it is reset The internal audio input master clock operating frequency is determined by N and P as follows N is interpreted as a 3 24 bit fractional number In DoM...

Page 324: ...rnally clocked logic when set Can only be cleared by Reset Since Main PLL may not be running during reset the power down signal to the Main PLL is overridden by reset Programming note An external host rather than the internal SPARCs should set this bit After the host sets this bit it should not perform a host access for at least 10 microseconds Video_PLL_Off 30 Power down video out PLL and interna...

Page 325: ...ns or pending operations Clock_Buf_Disable 11 also disables the MIclock and MOclock buffer inside AIO Clock_Buf_Disable 10 also disables VIN1Clock VIN2Clock VOUTClock the PTS clock is not disabled This field is reset to 0x0000 Wake Up Source Register Memory Space Address 0xC20004 Note The Wake Up Source register at control bus address 0xC20004 is used to enable or disable wake up events It is rese...

Page 326: ...the DMN 8600 asynchronously monitors the H_CS pin and generates a reset If the slave host interface is not selected by the Mode pins then this function is disabled The toggling of H_CS must be part of a legal DoMiNo access cycle otherwise the chip may hang after wake up 1394 wake up event When the DMN 8600 is in power down mode and 1394 wake up is enabled the DMN 8600 asynchronously monitors the L...

Page 329: ...The DMN 8600 processor implements a JTAG boundary scan interface in accordance with IEEE 1149 1 The optional TRST pin is provided to simplify resetting the tap controller in systems that do not use the JTAG port The tap controller must be reset after power up to enable normal processor operation Note The Tap Controller is not reset by RST DMN 8600 boundary scan supports only board level testing fo...

Page 330: ...in the test logic reset state The instruction loaded instead selects a 32 bit data register set to 0x1FFFFFFF when exiting the Capture DR state between TDI and TDO 17 2 Boundary Scan Chain Cells The Boundary Scan Chain Cells are listed in Table 17 2 Cell 1 is closest to TDO cell 595 is closest to TDI Note There are two flip flops for each pad on the chain one control flip flop and one data flip fl...

Page 331: ...ype 0 Control CTRL 1 U1 ATAPI_DMAACK IN OUT 2 Control CTRL 3 R4 ATAPI_DATA 0 IN OUT 4 Control CTRL 5 T2 ATAPI_DATA 13 IN OUT 6 Control CTRL 7 R3 ATAPI_DATA 1 IN OUT 8 Control CTRL 9 T1 ATAPI_DIOW OUT 10 Control CTRL 11 R2 ATAPI_DATA 12 IN OUT 12 Control CTRL 13 P4 ATAPI_DATA 2 IN OUT 14 Control CTRL 15 R1 ATAPI_DATA 11 IN OUT 16 Control CTRL 17 P3 ATAPI_DATA 3 IN OUT 18 Control CTRL 19 P2 ATAPI_DA...

Page 332: ...trol CTRL 27 N2 ATAPI_DATA 6 IN OUT 28 Control CTRL 29 N1 ATAPI_DATA 7 IN OUT 30 Control CTRL 31 M4 ATAPI_DATA 8 IN OUT 32 DUMMY N A 33 DUMMY N A 34 DUMMY N A 35 DUMMY N A 36 DUMMY N A 37 DUMMY N A 38 DUMMY N A 39 DUMMY N A 40 DUMMY N A 41 DUMMY N A 42 DUMMY N A 43 DUMMY N A 44 DUMMY N A 45 DUMMY N A 46 DUMMY N A 47 DUMMY N A Table 17 2 Boundary Scan Chain Cells Cont Cell Pin Name Type ...

Page 333: ...Y_DATA 3 IN OUT 54 DUMMY N A 55 DUMMY N A 56 Control CTRL 57 M1 BIO_LREQ OUT 58 DUMMY N A 59 DUMMY N A 60 Control CTRL 61 L4 BIO_LPS OUT 62 Control CTRL 63 L3 BIO_PHY_DATA 1 IN OUT 64 Control CTRL 65 L1 BIO_PHY_CLK IN 66 Control CTRL 67 L2 BIO_PHY_CTL 1 IN OUT 68 Control CTRL 69 K4 BIO_LINK_ON IN 70 Control CTRL 71 K3 BIO_PHY_DATA 7 IN OUT 72 Control CTRL Table 17 2 Boundary Scan Chain Cells Cont ...

Page 334: ...rol CTRL 77 J1 BIO_PHY_DATA 4 IN OUT 78 Control CTRL 79 J2 BIO_PHY_DATA 0 IN OUT 80 Control CTRL 81 J3 BIO_PHY_CTL 0 IN OUT 82 DUMMY N A 83 DUMMY N A 84 DUMMY N A 85 DUMMY N A 86 DUMMY N A 87 DUMMY N A 88 DUMMY N A 89 DUMMY N A 90 DUMMY N A 91 DUMMY N A 92 DUMMY N A 93 DUMMY N A 94 DUMMY N A 95 DUMMY N A 96 DUMMY N A 97 DUMMY N A Table 17 2 Boundary Scan Chain Cells Cont Cell Pin Name Type ...

Page 335: ...N A 103 DUMMY N A 104 Control CTRL 105 H1 VO_CLK IN OUT 106 DUMMY N A 107 DUMMY N A 108 DUMMY N A 109 DUMMY N A 110 Control CTRL 111 J4 VO_D 0 OUT 112 DUMMY N A 113 DUMMY N A 114 DUMMY N A 115 DUMMY N A 116 Control CTRL 117 H2 VO_D 1 OUT 118 Control CTRL 119 H3 VO_D 2 OUT 120 Control CTRL 121 H4 VO_D 3 OUT 122 Control CTRL Table 17 2 Boundary Scan Chain Cells Cont Cell Pin Name Type ...

Page 336: ...Control CTRL 129 F1 VO_D 7 OUT 130 Control CTRL 131 F2 VO_D 8 OUT 132 Control CTRL 133 G4 VO_D 9 OUT 134 Control CTRL 135 E1 VO_D 10 OUT 136 Control CTRL 137 F3 VO_D 11 OUT 138 Control CTRL 139 E2 VO_D 12 OUT 140 Control CTRL 141 D1 VO_D 13 OUT 142 Control CTRL 143 F4 VO_D 15 OUT 144 DUMMY N A 145 DUMMY N A 146 Control CTRL 147 E3 VO_D 14 OUT Table 17 2 Boundary Scan Chain Cells Cont Cell Pin Name...

Page 337: ...DUMMY N A 152 DUMMY N A 153 DUMMY N A 154 DUMMY N A 155 DUMMY N A 156 DUMMY N A 157 DUMMY N A 158 DUMMY N A 159 DUMMY N A 160 DUMMY N A 161 DUMMY N A 162 DUMMY N A 163 DUMMY N A 164 DUMMY N A 165 DUMMY N A 166 DUMMY N A 167 DUMMY N A 168 DUMMY N A 169 DUMMY N A 170 DUMMY N A 171 DUMMY N A 172 Control CTRL Table 17 2 Boundary Scan Chain Cells Cont Cell Pin Name Type ...

Page 338: ... C2 VI_D 4 IN 178 DUMMY N A 179 DUMMY N A 180 Control CTRL 181 C3 VI_D 3 IN 182 Control CTRL 183 B2 VI_D 2 IN 184 Control CTRL 185 A1 VI_D 9 IN 186 Control CTRL 187 A2 VI_D 8 IN 188 Control CTRL 189 B3 VI_D 7 IN 190 Control CTRL 191 C4 VI_D 6 IN 192 DUMMY N A 193 DUMMY N A 194 DUMMY N A 195 DUMMY N A 196 DUMMY N A 197 DUMMY N A Table 17 2 Boundary Scan Chain Cells Cont Cell Pin Name Type ...

Page 339: ...Y N A 203 DUMMY N A 204 DUMMY N A 205 DUMMY N A 206 DUMMY N A 207 DUMMY N A 208 DUMMY N A 209 DUMMY N A 210 Control CTRL 211 A5 VI_CLK 0 IN 212 DUMMY N A 213 DUMMY N A 214 Control CTRL 215 A7 PLL_BYPASS IN 216 Control CTRL 217 A12 CLKO OUT 218 Control CTRL 219 B12 AI_SCLK IN OUT 220 DUMMY N A 221 DUMMY N A 222 Control CTRL Table 17 2 Boundary Scan Chain Cells Cont Cell Pin Name Type ...

Page 340: ...ontrol CTRL 229 D12 AI_D 1 IN 230 Control CTRL 231 A13 AI_MCLKO OUT 232 Control CTRL 233 B13 AO_MCLKO OUT 234 DUMMY N A 235 DUMMY N A 236 Control CTRL 237 C13 AI_D 0 IN 238 Control CTRL 239 B14 AO_IEC958 OUT 240 Control CTRL 241 D13 AO_FSYNC OUT 242 DUMMY N A 243 DUMMY N A 244 Control CTRL 245 A14 AO_SCLK OUT 246 DUMMY N A 247 DUMMY N A Table 17 2 Boundary Scan Chain Cells Cont Cell Pin Name Type ...

Page 341: ...MMY N A 252 DUMMY N A 253 DUMMY N A 254 Control CTRL 255 D14 AO_D 0 OUT 256 DUMMY N A 257 DUMMY N A 258 DUMMY N A 259 DUMMY N A 260 DUMMY N A 261 DUMMY N A 262 Control CTRL 263 A15 AO_D 3 OUT 264 DUMMY N A 265 DUMMY N A 266 DUMMY N A 267 DUMMY N A 268 DUMMY N A 269 DUMMY N A 270 DUMMY N A 271 DUMMY N A 272 DUMMY N A Table 17 2 Boundary Scan Chain Cells Cont Cell Pin Name Type ...

Page 342: ... 278 DUMMY N A 279 DUMMY N A 280 DUMMY N A 281 DUMMY N A 282 DUMMY N A 283 DUMMY N A 284 DUMMY N A 285 DUMMY N A 286 DUMMY N A 287 DUMMY N A 288 DUMMY N A 289 DUMMY N A 290 Control CTRL 291 A16 SDRAM_WE OUT 292 Control CTRL 293 C15 SDRAM_CKE OUT 294 Control CTRL 295 B16 SDRAM_RAS OUT 296 Control CTRL 297 B17 SDRAM_CAS OUT Table 17 2 Boundary Scan Chain Cells Cont Cell Pin Name Type ...

Page 343: ... OUT 304 Control CTRL 305 B18 SDRAM_A 4 OUT 306 Control CTRL 307 A19 SDRAM_A 0 OUT 308 Control CTRL 309 C18 SDRAM_A 6 OUT 310 Control CTRL 311 B19 SDRAM_A 1 OUT 312 Control CTRL 313 A20 SDRAM_A 5 OUT 314 Control CTRL 315 E17 SDRAM_A 12 OUT 316 Control CTRL 317 D18 SDRAM_A 8 OUT 318 Control CTRL 319 C19 SDRAM_A 10 OUT 320 Control CTRL 321 B20 SDRAM_A 7 OUT 322 Control CTRL Table 17 2 Boundary Scan ...

Page 344: ...330 Control CTRL 331 D20 SDRAM_DQ 24 IN OUT 332 Control CTRL 333 E19 SDRAM_DQ 25 IN OUT 334 Control CTRL 335 F18 SDRAM_DQ 26 IN OUT 336 Control CTRL 337 G17 SDRAM_DQ 27 IN OUT 338 Control CTRL 339 E20 SDRAM_DQS 3 IN OUT 340 Control CTRL 341 F19 SDRAM_DQ 30 IN OUT 342 Control CTRL 343 G18 SDRAM_DQ 28 IN OUT 344 Control CTRL 345 H17 SDRAM_DQ 29 IN OUT 346 Control CTRL 347 F20 SDRAM_DQ 31 IN OUT Tabl...

Page 345: ...RL 355 H19 SDRAM_DQ 23 IN OUT 356 Control CTRL 357 H18 SDRAM_DQ 22 IN OUT 358 Control CTRL 359 J17 SDRAM_DQ 21 IN OUT 360 Control CTRL 361 J18 SDRAM_DQ 20 IN OUT 362 Control CTRL 363 J19 SDRAM_DQS 2 IN OUT 364 Control CTRL 365 J20 SDRAM_DQ 19 IN OUT 366 Control CTRL 367 K17 SDRAM_DQ 18 IN OUT 368 Control CTRL 369 K18 SDRAM_DQ 17 IN OUT 370 Control CTRL 371 K19 SDRAM_DQ 16 IN OUT 372 Control CTRL T...

Page 346: ...1 IN OUT 380 Control CTRL 381 L20 SDRAM_DQ 13 IN OUT 382 Control CTRL 383 M20 SDRAM_DQ 10 IN OUT 384 Control CTRL 385 M19 SDRAM_DQS 1 IN OUT 386 Control CTRL 387 M18 SDRAM_DQ 14 IN OUT 388 Control CTRL 389 M17 SDRAM_DQ 12 IN OUT 390 Control CTRL 391 N19 SDRAM_DQ 9 IN OUT 392 Control CTRL 393 N18 SDRAM_DQ 15 IN OUT 394 Control CTRL 395 N17 SDRAM_DQM 0 OUT 396 Control CTRL 397 N20 SDRAM_CLK 0 OUT Ta...

Page 347: ...IN OUT 404 Control CTRL 405 R20 SDRAM_DQ 5 IN OUT 406 Control CTRL 407 P17 SDRAM_DQ 4 IN OUT 408 Control CTRL 409 R19 SDRAM_DQS 0 IN OUT 410 Control CTRL 411 T20 SDRAM_DQ 3 IN OUT 412 Control CTRL 413 R18 SDRAM_DQ 2 IN OUT 414 Control CTRL 415 T19 SDRAM_DQ 1 IN OUT 416 Control CTRL 417 R17 SDRAM_DQ 0 IN OUT 418 DUMMY N A 419 DUMMY N A 420 DUMMY N A 421 DUMMY N A 422 Control CTRL Table 17 2 Boundar...

Page 348: ... A 429 DUMMY N A 430 DUMMY N A 431 DUMMY N A 432 Control CTRL 433 V20 SIO_UART1_RTS OUT 434 Control CTRL 435 U18 SIO_SPI_MOSI OUT 436 Control CTRL 437 V19 SIO_SCL IN OUT 438 Control CTRL 439 W20 SIO_UART2_RX IN 440 Control CTRL 441 V18 SIO_SPI_CS 1 OUT 442 Control CTRL 443 W19 SIO_UART1_RX IN OUT 444 Control CTRL 445 Y20 SIO_IRRX IN 446 Control CTRL 447 Y19 SIO_SPI_CS 0 OUT Table 17 2 Boundary Sca...

Page 349: ...Control CTRL 453 Y18 SIO_SDA IN OUT 454 Control CTRL 455 W17 SIO_IRTX2 OUT 456 Control CTRL 457 V16 SIO_SPI_CS 2 OUT 458 Control CTRL 459 Y17 SIO_SPI_CLK OUT 460 Control CTRL 461 U14 SIO_IRTX1 OUT 462 DUMMY N A 463 DUMMY N A 464 DUMMY N A 465 DUMMY N A 466 DUMMY N A 467 DUMMY N A 468 DUMMY N A 469 DUMMY N A 470 DUMMY N A 471 DUMMY N A 472 Control CTRL Table 17 2 Boundary Scan Chain Cells Cont Cell...

Page 350: ...DUMMY N A 477 DUMMY N A 478 DUMMY N A 479 DUMMY N A 480 DUMMY N A 481 DUMMY N A 482 DUMMY N A 483 DUMMY N A 484 DUMMY N A 485 DUMMY N A 486 DUMMY N A 487 DUMMY N A 488 DUMMY N A 489 DUMMY N A 490 DUMMY N A 491 DUMMY N A 492 DUMMY N A 493 DUMMY N A 494 DUMMY N A 495 DUMMY N A 496 DUMMY N A 497 DUMMY N A Table 17 2 Boundary Scan Chain Cells Cont Cell Pin Name Type ...

Page 351: ...1 DUMMY N A 502 DUMMY N A 503 DUMMY N A 504 DUMMY N A 505 DUMMY N A 506 DUMMY N A 507 DUMMY N A 508 DUMMY N A 509 DUMMY N A 510 DUMMY N A 511 DUMMY N A 512 DUMMY N A 513 DUMMY N A 514 DUMMY N A 515 DUMMY N A 516 DUMMY N A 517 DUMMY N A 518 DUMMY N A 519 DUMMY N A 520 DUMMY N A 521 DUMMY N A 522 DUMMY N A Table 17 2 Boundary Scan Chain Cells Cont Cell Pin Name Type ...

Page 352: ...MMY N A 527 DUMMY N A 528 DUMMY N A 529 DUMMY N A 530 DUMMY N A 531 DUMMY N A 532 DUMMY N A 533 DUMMY N A 534 DUMMY N A 535 DUMMY N A 536 DUMMY N A 537 DUMMY N A 538 DUMMY N A 539 DUMMY N A 540 DUMMY N A 541 DUMMY N A 542 DUMMY N A 543 DUMMY N A 544 DUMMY N A 545 DUMMY N A 546 DUMMY N A 547 DUMMY N A Table 17 2 Boundary Scan Chain Cells Cont Cell Pin Name Type ...

Page 353: ... N A 552 DUMMY N A 553 DUMMY N A 554 DUMMY N A 555 DUMMY N A 556 DUMMY N A 557 DUMMY N A 558 DUMMY N A 559 DUMMY N A 560 DUMMY N A 561 DUMMY N A 562 Control CTRL 563 M16 MCONFIG 0 IN 564 DUMMY N A 565 DUMMY N A 566 DUMMY N A 567 DUMMY N A 568 DUMMY N A 569 DUMMY N A 570 DUMMY N A 571 DUMMY N A 572 Control CTRL Table 17 2 Boundary Scan Chain Cells Cont Cell Pin Name Type ...

Page 354: ...T 578 Control CTRL 579 Y1 ATAPI_RESET OUT 580 Control CTRL 581 W2 ATAPI_INTRQ IN 582 Control CTRL 583 V3 ATAPI_DIOR OUT 584 Control CTRL 585 W1 ATAPI_DMARQ IN 586 Control CTRL 587 V2 ATAPI_ADDR 1 IN OUT 588 Control CTRL 589 U3 ATAPI_ADDR 3 OUT 590 Control CTRL 591 V1 ATAPI_ADDR 2 OUT 592 Control CTRL 593 U2 ATAPI_DATA 14 IN OUT 594 Control CTRL 595 T3 ATAPI_IORDY IN Table 17 2 Boundary Scan Chain ...

Page 355: ...ection 18 3 Pin Description Section 18 4 Package Mechanical Specifications 18 1 Electrical Specifications This section specifies the electrical requirements for the DMN 8600 processor Table 18 1 Absolute Maximum Ratings1 Parameters Value Units Supply Voltages VDD_5 For 5V tolerant signals 0 5 to 5 5 V VDD_2 5 DDR SDRAM DDR only 0 25 to 2 75 V VDD_2 5 SDR SDRAM SDR only 0 3 to 3 6 V VDD_3 3 I O sup...

Page 356: ...or 10 seconds max C 1 Exposure to stresses beyond those listed in this table may result in device unreliability permanent damage or both Table 18 1 Absolute Maximum Ratings1 Cont Parameters Value Units Table 18 2 Operating Conditions Parameters Min Typical Max Unit Supply Voltages VDD_5 For 5V tolerant signals 4 75 5 0 5 25 V VDD_2 5 DDR SDRAM DDR only 2 375 2 5 2 625 V VDD_2 5 SDR SDRAM SDR only ...

Page 357: ...ividual signal 2 4 V VOL Low level output voltage VDD_3 3 Min IOL drive level of individual signal 0 5 V IIH High level input current VDD_3 3 and VDD_2 5 Max VIN VDD 10 µA IIL Low level input current VDD_3 3 and VDD_2 5 Max VIN 0 V 10 µA IOZ Output leakage current Hi Z output driven to 0 V and 3 15V 10 10 µA IOZM Output leakage current SDRAM pins Hi Z output driven to 0 V and VDD 10 10 µA IDD_2 5 ...

Page 358: ...SDRAM Interface AC Timing page 18 20 Section 18 2 5 CD Interface Timing page 18 26 Section 18 2 6 IDC Interface Timing page 18 27 Section 18 2 7 Audio Timing page 18 30 Section 18 2 8 UART Interface Timing page 18 31 Section 18 2 9 Video Interface Timing page 18 32 Section 18 2 10 IR Interface Timing page 18 35 Section 18 2 11 JTAG Interface Signal Timing page 18 36 Section 18 2 12 ATAPI AC Timing...

Page 359: ...igured to be edge or level sensitive and must be asserted for at least two clock cycles as shown in Figure 18 2 Table 18 4 Miscellaneous Timing Values Sym bol Description Timing Value 13 5 MHz Crystal Unit Timing Value 27 MHz Crystal Unit Min Max Min Max TCYC CLKI cycle time 74 07 ns 37 04 ns THIGH CLKI high time 33 ns 16 5 ns TLOW CLKI low time 33 ns 16 5 ns T31 CLKO output delay with respect to ...

Page 360: ... either a self paced or device paced protocol The master interface can also multiplex address and data lines Unless otherwise noted cycle type variations are independent of each other and can be mixed and matched as the system designer sees fit This accounts for a total of nine possible variations as shown in Figure 18 3 through Figure 18 11 and described in Table 18 5 Figure 18 3 Self Paced Async...

Page 361: ...18 4 Self Paced Async Master Write Cycle in SRAM Mode Figure 18 5 Self Paced Async Master Read Cycle in 68K Mode TCS M_A O M_CS O M_UWE LWE O M_OE O M_D O TDS Twrite_data_valid TBH Twrite_data_hold TCS TDS TBH TholdCS Tdata_valid_begin2 Tdata_valid_end1 Tdata_valid_begin1 M_A O M_CS O M_R W O M_LDS UDS O M_D I ...

Page 362: ...eserved Figure 18 6 Self Paced Async Master Write Cycle in 68K Mode Figure 18 7 Device Paced Async Master Read Cycle in 68K Mode TBH TCS Twrite_data_valid Twrite_data_hold M_A O M_R W O M_LDS UDS O M_CS O M_D O TDS TDS TholdCS M_A O M_R W O M_LDS UDS O M_CS O M_D O M_DTACK I M_WAIT I TCS TSU TBH TDTPW ...

Page 363: ...9 Copyright 2001 2002 by LSI Logic Corporation All rights reserved Figure 18 8 Device Paced Async Master Write Cycle in 68K Mode TBH TCS Twrite_data_valid M_A O M_WR O M_CS O M_D O M_DTACK I M_WAIT I M_LDS UDS O TDS Twrite_data_hold TDTPW ...

Page 364: ... Specifications Copyright 2001 2002 by LSI Logic Corporation All rights reserved Figure 18 9 Device Paced Async Master Read Cycle in SRAM Mode TBH TCS TDS TholdCS TDTPW M_A O M_UWE LWE O M_CS O M_D I M_DTACK I M_WAIT I M_OE O TSU ...

Page 365: ... Copyright 2001 2002 by LSI Logic Corporation All rights reserved Figure 18 10 Device Paced Async Master Write Cycle in SRAM Mode TBH TCS Twrite_data_valid TDS TDTPW M_A O M_UWE LWE O M_CS O M_D O M_DTACK I M_WAIT I M_OE O Twrite_data_hold ...

Page 366: ...LE O M_CS O M_UWE LWE O M_OE O M_D I O Low Addr Low Addr Middle Addr Data Data TPW TAH High Addr TDS TBH TholdCS Tdata_valid_end1 Table 18 5 Async Host Master Timing Parameters Master Mode Only Master replaces Slave Parameters Description Min Max TPW M_ALE pulse width from M_A and M_ALE asserted to fall of M_ALE This can be treated as setup time AS clock cycles 2 ns AS clock cycles 2 ns TAH Time f...

Page 367: ... pulse width 2 clock cycles Tdata_valid_e nd n 1 Delay for M_A and R W stable to end of nth read data during bursts for single access TholdCS is applicable DT n 1 BDT 1 3 clock cycles Twrite_data_v alid Delay from write strobes M_UWE M_LWE M_UDS M_LDS falling to write data valid DS clock cycles 2 ns DS clock cycles 6 ns Twrite_data_h old Write data hold time after data strobes pull up BH clock cyc...

Page 368: ...s 7 ns CS clock cycles 2 ns TDS Delay from M_A to fall of data strobes DS clock cycles 4 ns DS clock cycles 4 ns Tdata_valid_begin n 1 1 The parameters Tdata_valid_begin n and Tdata_valid_end n represent the minimum possible window dur ing which the data pins must be stable Delay from M_A and M_RD WR stable to stable nth read data applicable for bursts and single access DT n 1 BDT 1 clock cycles 6...

Page 369: ... time with respect to WR falling 3 cycles 14 ns T3 H_WAIT assertion period 2 cycles T4 H_DTACK output delay time with respect to WR falling 3 cycles 14 ns T5 H_DTACK assertion period 2 cycles T6 Output delay from WR rising to H_WAIT 3 state 2 cycles 3 cycles T7 Output delay from WR rising to H_DTACK 3 state 2 cycles 3 cycles T8 WR hold time with respect to WAIT rising 3 0 ns T9 WR hold time with r...

Page 370: ... 0 hold time with respect to WR falling 2 0 ns T12 H_DATA 31 0 setup time with respect to WR rising 3 0 ns T13 H_DATA 31 0 hold time with respect to WR rising 2 0 ns T14 H_CS high period 2 cycles 1 H_WAIT and H_DTACK are pulled up by an internal pull up on 3 state Table 18 7 I Mode Write AC Timing Parameters1 Cont Symbol Description Timing Value Min Max T3 H_CS I H_RD I H_WAIT O H_DTACK O H_ADDR 2...

Page 371: ...3 cycles 14 ns T4 H_WAIT assertion period 2 cycles T5 H_DTACK output delay time with respect to RD falling 3 cycles 14 ns T6 H_DTACK assertion period 2 cycles T7 Delay from H_WAIT rising to data valid 1 cycle T8 Delay from RD rising to data float 2 cycles T9 Output delay from RD rising to H_WAIT 3 stated 2 cycles 3 cycles T10 Output delay from RD rising to H_DTACK 3 stated 2 cycles 3 cycles T11 RD...

Page 372: ...ol Description Timing Value Min Max T1 WR setup time with respect to H_CS falling 3 0 ns T2 WR hold time with respect to H_CS rising 2 0 ns T3 H_WAIT output delay time with respect to H_CS falling 3 cycles 14 ns T4 H_WAIT assertion period 2 cycles T5 DTACK output delay time with respect to WR falling 3 cycles 14 ns T6 DTACK assertion period 2 cycles T7 Output delay from H_CS rising to H_WAIT 3 sta...

Page 373: ...H_CS falling 3 0 ns T12 H_ADDR 2 0 hold time with respect to H_CS falling 2 0 ns T13 H_DATA 31 0 setup time with respect to H_CS rising 3 0 ns T14 H_DATA 31 0 hold time with respect to H_CS rising 2 0 ns 1 H_WAIT and H_DTACK are pulled up by an internal pull up on 3 state Table 18 9 M Mode Write AC Timing Parameters1 Cont Symbol Description Timing Value Min Max T4 H_CS I H_RD WR I H_WAIT O H_DTACK...

Page 374: ...g of CLK and CLK is used as the reference Table 18 10 M Mode Read AC Timing Parameters1 Symbo l Description Timing Value Min Max T1 H_ADDR 2 0 input setup time with respect to H_CS falling 3 0 ns T2 H_ADDR 2 0 input hold time with respect to H_CS falling 2 0 ns T3 H_WAIT output delay time with respect to H_CS falling 3 cycles 14 ns T4 H_WAIT assertion period 2 cycles T5 H_DTACK output delay time w...

Page 375: ... 18 16 SDRAM Clock LOW and HIGH Period Definition T2 TCYC SDRAM_CLK Clock High Low Period In SDR Mode Clock High Low Period In DDR Mode SDRAM_CLK SDRAM_CLK 2 0 V 0 8 V THIGH TLOW T1 Table 18 11 Clock Signals to SDRAM Timing Symbol Description Min Max Units TCYC Clock cycle period in SDR or DDR mode 81 148 5 MHz THIGH Clock HIGH period in SDR mode 0 4 0 6 TCYC TLOW Clock LOW period in SDR mode 0 4 ...

Page 376: ...l pins include SDRAM_CAS SDRAM_RAS SDRAM_WE and address pins include SDRAM_A 15 0 all of which output of the DMN 8600 SDRAM_DQ 31 0 is driven from DMN 8600 for writes to SDRAM 18 2 4 3 DMN 8600 Reading from SDRAM in SDR Mode SDRAM reading like writing is also in burst mode CAS latency for a DRAM read is programmed once during initialization of the memory chip For SDR mode it can be 2 or 3 T2 T1 SD...

Page 377: ...mable phase shift is utilized to capture the input data on SDRAM_DQ So the value of T3 can be negative that is data can appear on the cycle after the one indicated by the CAS latency value The internal programmable clock will be able to capture the data up to the specified delay 18 2 4 4 DMN 8600 Writing to SDRAM in DDR Mode For DDR mode when writing into the SDRAM DMN 8600 drives SDRAM_DQS signal...

Page 378: ...RAM_CAS SDRAM_RAS SDRAM_WE and address pins include SDRAM_A 15 0 all of which are outputs of DoMiNo SDRAM_DQ 31 0 and SDRAM_DQS 3 0 are driven from DMN 8600 for writes to SDRAM T2 T1 SDRAM_CLK O SDRAM_CLK O SDRAM_DQS 3 0 I O Control Addr Pins O SDRAM_DQ 31 0 I O T3 T4 T4 T5 T5 Table 18 14 DMN 8600 Write to SDRAM DDR Mode Parameters Symbol Description Min Max Unit T1 Control Addr pins output delay ...

Page 379: ...sed to sample data Figure 18 20 DMN 8600 Read from SDRAM in DDR Mode Please note the following related information Control pins include SDRAM_CAS SDRAM_RAS SDRAM_WE and address pins include SDRAM_A 15 0 all of which are outputs of DoMiNo T2 T1 SDRAM_CLK O SDRAM_CLK O SDRAM_DQS 3 0 I O Control Addr Pins O SDRAM_DQ 31 0 I O T3 T4 T4 T3 Table 18 15 DMN 8600 Read from SDRAM DDR mode Parameters Symbol ...

Page 380: ...igure 18 21 and Table 18 16 show the timing for the CD signal input Figure 18 21 CD Interface Timing T1 CD_BCK I CD_LRCK I CD_Data I CD_C2PO I 70 50 30 TCYC THIGH TLOW T2 Table 18 16 CD Input Timing Symbol Description Min Max Units TCYC Cycle clock period 100 THIGH CD_BCK HIGH pulse width 50 ns TLOW CD_BCK LOW pulse width 50 ns T1 CD_DATA CD_LRCK CD_C2PO setup 10 ns T2 CD_DATA CD_LRCK CD_C2PO hold...

Page 381: ...e 18 17 IDC Master Timing See Figure 18 23 and Table 18 18 Figure 18 22 IDC Interface AC Slave Timing TSTART SIO_SCL I SIO_SDA I O THD O TSTOP Data In Data Out TSU I THIGH TLOW THD I TCYC TVALID O Table 18 17 IDC Interface Slave Timing Parameter Param Description IDC Design Values in sysclk cycles Min Max THIGH High period of SIO_SCL I M S 1 R 1 3 TLOW Low period of SIO_SCL I M S 1 F 1 2 TCYC Cloc...

Page 382: ...y from SIO_SDA I falling to next SIO_SCL I rising M S 1 F R 1 2 TSTOP Delay from SIO_SCL I rising to SIO_SDA I rising M S 1 2 TSU I SIO_SDA I set up time before SIO_SCL I rising M S 1 F R for SIO_SDA I falling only 0 THD I SIO_SDA I hold time after SIO_SCL I rising M S 1 for SIO_SDA I rising after S 1 R F 1 for SIO_SDA I falling after 3 TVALID O Delay from SIO_SCL I falling to SIO_SDA O valid 9 S ...

Page 383: ... Param Description IDC Design Values in sysclk cycles Min Max THIGH High period of SIO_SCL O 8 2 C S 1 R 7 2 C S 1 R 1 TLOW Low period of SIO_SCL O 2 C TCYC Clock period of SIO_SCL O 8 4 C S 1 R 7 4 C S 1 R 1 TSTART Delay from SIO_SDA O falling to next SIO_SCL O falling C TSTOP Delay from SIO_SCL O rising to SIO_SDA O rising 10 2 C S 1 R 9 2 C S 1 R 1 TSU I SIO_SDA I set up time before SIO_SCL O r...

Page 384: ...Input Output AC Timing Note Diagram shown is with falling driving edge rising sampling edge The same parameters are valid for rising driving edge falling sample edge T1 Driving Edge AI_MCLKO O AO_MCLKO O AI_SCLK I O AO_SCLK O FSYNC Data O FSYNC Data I Sampling Edge 70 50 30 TCYC THIGH TLOW T4 T2 T3 Table 18 19 Audio Input Output AC Timing Parameters Symbol Description Min1 Typ Max Unit TCYC MCLK c...

Page 385: ... data input to sampling edge SCLK hold 10 ns T42 SCLK period Absolute 403 ns T42 SCLK period Relative Less than four data pins active IEC958 active R958 0 and OTim 0 Four data pins active Less than four data pins active 6 cycles 9 cycles 5 cycles ns 1 Cycles refers to internal system clock cycles 2 Four data pins are active if ChCnt 3 or FrForm 1 or FrForm 0 ChCnt 4 See Audio Output Control regist...

Page 386: ... and Table 18 21 show the AC timing for the DMN 8600 device Video interface Figure 18 26 AC Timing for Video Input Stream at VI_CLK 0 Table 18 20 UART Interface AC Timing Symbol Description Value T1 T2 T3 T4 Minimum data valid time for signals on SIO_UART pins 3 sysclk cycles T1 VI_CLK 0 I VI_D 9 2 I VI_VSYNC 0 I 70 50 30 TC THIGH TLOW T2 T3 T4 Valid ...

Page 387: ...Timing Value Unit Min Typ Max TC Cycle time 13 46 74 25 MHz 37 03 27 MHz ns T1 Rise time 0 5 5 0 27 MHz 2 0 74 25 MHz ns T2 Fall time 0 5 5 0 27 MHz 2 0 74 25 MHz ns T3 Input data setup time VI_D 9 2 and VI_VSYNC 0 before the rising edge of VI_CLK 0 3 0 T4 Input data hold time for VI_D 9 2 VI_VSYNC 0 after the rising edge of VI_CLK 0 0 ns Table 18 22 Video Out Clock Source OSync Video Out PLL Sour...

Page 388: ...o output clock should not be used by the system Tf 80 50 20 VO_CLK I O VO_D 15 0 O THIGH TLOW Tr Td2 Td1 TCYC Table 18 23 Video Output AC Timing Parameters at VO_CLK Symbol Description Timing Value Unit Min Typ Max tC Cycle time 13 46 37 03 ns tr Rise time 0 5 5 0 27 MHz 2 0 74 25 MHz ns tf Fall time 0 5 5 0 27 MHz 2 0 74 25 MHz ns td1 Output data valid time VO_D 15 0 after the rising edge of VO_C...

Page 389: ...ms with the programmed pulse length and period characteristics while for receive it simply measures the period and duty cycle of incoming pulses Since there is no generic IR protocol which can be described the waveforms shown below illustrate how the values read written from various IR registers relate to the actual waveforms themselves Waveforms for two common protocols NCR and Philips RC 5 are a...

Page 390: ...cles 0x0 1 carrier cycles 0xff 1 carrier cycles T3 IRTX carrier wave period user can program period of carrier waveform in units of system clock cycles 0x0 1 sys clock cycles 0x3fff 1 sys clock cycles T4 IRTX modulated signal pulse High user can program duty cycle of carrier waveform in units of system clock cycles 0x0 1 sys clock cycles 0x1fff 1 sys clock cycles T5 IRRX receive tick period User c...

Page 391: ...face AC Timing Values Symbol Description Timing Value ns Min Max TCYC TCK period 100 0 THIGH TCK HIGH time 40 0 TLOW TCK LOW time 40 0 T4 TDI TMS RST setup time to TCK 10 0 T5 TDI TMS RST hold time from TCK 5 0 T6 TDO delay time from TCK 2 0 T7 TDO hold time from CLK 1 0 T4 70 50 30 TCK I Note TRST is an asynchronous reset TDI TMS TRST I TDO O TCYC THIGH TLOW T5 T7 T6 ...

Page 392: ...e time min 480 150 120 tC ATAPI_DMAACK to ATAPI_DMARQ delay max 1 200 100 80 tD ATAPI_DIOR ATAPI_DIOW 16 bit min 215 80 70 RWTime C2 tE ATAPI_DIOR data access max 250 150 60 tF ATAPI_DIOR data hold min 5 5 5 tGr ATAPI_DIOR data setup min 100 30 20 tGw ATAPI_DIOW data setup min 100 30 20 tH ATAPI_DIOW data hold min 20 15 10 RWHold C ATAPI_DMARQ I ATAPI_DMAACK O ATAPI_DIOW DIOR O ATAPI_DATA 15 0 ATA...

Page 393: ...ATAPI_DIOR negated pulse width min 50 50 25 RWWidth C tKw ATAPI_DIOW negated pulse width min 215 50 25 RWWidth C tLr ATAPI_DIOR to ATAPI_DMARQ delay max 120 40 35 tLw ATAPI_DIOW to ATAPI_DMARQ delay max 40 40 35 tZ ATAPI_DMAACK to 3 state max 20 25 25 1 This timing only applies to a single DMA transfer 2 C is the system clock cycle time Table 18 26 ATAPI DMA Protocol Timing Cont Symbol Parameters ...

Page 394: ...time min 600 383 240 180 120 t1 Address valid to ATAPI_DIOR ATAPI_DIOW setup min 70 RWSetup C 50 RWSetup C 30 RWSetup C 30 RWSetup C 25 RWSetup C t2 ATAPI_DIOR ATAPI_DIOW 16 bit min 165 RWTime C 125 RWTime C 100 RWTime C 80 RWTime C 70 RWTime C t2i ATAPI_DIOR ATAPI_DIOW recovery time min RWRcv C RWRcv C RWRcv C 70 RWRcv C 25 RWRcv C t3 ATAPI_DIOW data setup min 60 45 30 30 20 T6z T6 T0 ATAPI_DIOR ...

Page 395: ...d C t5 ATAPI_DIOR data setup min 50 35 20 20 20 t6 ATAPI_DIOR data hold min 5 5 5 5 5 t6z ATAPI_DIOR data 3 state max 30 30 30 30 30 t9 ATAPI_DIOR ATAPI_DIOW to address valid hold min 20 RWHold C 15 RWHold C 10 RWHold C 10 RWHold C 10 RWHold C tRd Read data valid to ATAPI_IORDY active if ATAPI_IORDY initially low after tA min 0 0 0 0 0 tA ATAPI_IORDY setup time min 35 35 35 35 35 tB ATAPI_IORDY pu...

Page 396: ...t Timing Symbol Description Light Loading 50 MHz 1 Heavy Loading 27 16 MHz Min Max Min Max Input Transition Time 2 0 ns 5 0 ns Ouput Load 10 pF 60 pF TCYC SD_CLK period 20 ns 37 ns THIGH SD_CLK high 9 ns 16 ns SD_CLK I SD_ACK I SD_DATA 7 0 I SD_WRREQ O SD_RDREQ O SD_SECSTART I 70 50 30 T7 SD_SECSTART O SD_DATA 7 0 O SD_ERROR I TCYC THIGH TLOW T4 T6 T4 T3 T6 T6 ...

Page 397: ...ow 9 ns 16 ns T3 SD_ERROR SD_SECSTART SD_ACK setup 6 ns 6 ns T4 SD_DATA setup 4 ns 3 ns T6 SD_ERROR SD_SECSTART SD_DATA SD_ACK hold 1 25 ns 1 25 ns T7 SD_WRREQ SD_RDREQ SD_DATA and SD_SECSTART output delay 3 ns 11 ns 4 ns 18 ns 1 Note Light loading 50 MHz is for point to point connections in a multi DMN 8600 configuration Table 18 28 SD Input Timing Cont Symbol Description Light Loading 50 MHz 1 H...

Page 398: ...PI_MOSI active 2 cycles 10 ns 2 cycles 30 ns T2 Assertion SIO_SPI_CS to SPI_CLK edge1 1 These values are programmed in the SPI Configuration register 0 ns 91 ns T3 Deassertion SPI_CLK edge to SIO_SPI_CS1 0 ns 91 ns T4 Setup time SIO_SPI_MISO to SPI_CLK edge 3 cycles T5 Hold time SIO_SPI_MISO to SPI_CLK edge 3 cycles 70 50 30 TCYC THIGH TLOW T2 T1 Table 18 30 1394 AC Timing Parameters Param Descrip...

Page 399: ... 1 outputs valid 0 5 13 5 ns tpd2 Delay time BIO_PHY_CLK input high to subsequent instance s of BIO_PHY_DATA 0 7 and BIO_PHY_CTL 0 1 outputs valid 0 5 13 5 ns tpd3 Delay time BIO_PHY_CLK input high to BIO_PHY_DATA 0 7 and BIO_PHY_CTL 0 1 invalid high impedance 0 5 13 5 ns tpsu Setup time BIO_PHY_DATA 0 7 BIO_PHY_CTL 0 1 and BIO_LREQ inputs before BIO_PHY_CLK 6 0 ns tph Hold time BIO_PHY_DATA 0 7 B...

Page 400: ...A 0 7 and BIO_PHY_CTL 0 1 outputs valid 1 10 tld2 Delay time BIO_PHY_CLK input high to subsequent instance s of BIO_PHY_DATA 0 7 and BIO_PHY_CTL 0 1 outputs valid 1 10 tld3 Delay time BIO_PHY_CLK input high to BIO_PHY_DATA 0 7 and BIO_PHY_CTL 0 1 invalid high impedance 1 10 tlsu Setup time BIO_PHY_DATA 0 7 BIO_PHY_CTL 0 1 and BIO_LREQ inputs before BIO_PHY_CLK 6 tlh Hold time BIO_PHY_DATA 0 7 BIO_...

Page 401: ...rface Timing SBP timing diagrams are shown in figures Figure 18 39 through Figure 18 43 and are described in Table 18 33 Figure 18 39 SBP Clock Timing Figure 18 40 SBP Incoming Transfer POL 1 WRREQ 0 70 50 30 TCYC THIGH TLOW SBP_CLK I SBP_ACK I SBP_FRAME I O SBP_DATA 7 0 I O SBP_REQ O SBP_RD O T1 T9 T6 T5 T2 T4 T3 T8 T7 ...

Page 402: ...served Figure 18 41 SBP Outgoing Transfer POL 1 WRREQ 0 Figure 18 42 SBP Incoming Transfer POL 0 WRREQ 0 T1 SBP_CLK I SBP_ACK I SBP_FRAME I O SBP_DATA 7 0 I O SBP_REQ O SBP_RD O T9 T10 T5 T6 T11 T12 T13 T14 T1 SBP_CLK I SBP_ACK I SBP_FRAME I O SBP_DATA 7 0 I O SBP_REQ O SBP_RD O T9 T2 T5 T6 T3 T7 T8 T4 ...

Page 403: ...ng ns 27 16 MHz Min Max Min Max TCLK Clock period 20 37 ns THIGH Clock high time 9 16 ns TLOW Clock low time 9 16 ns T1 SBP_REQ output delay time 12 0 18 0 T2 SBP_RD output delay time 12 0 18 0 T3 SBP_DATA input setup time 3 0 3 0 T4 SBP_DATA input hold time 1 25 1 25 T5 SBP_ACK input setup time 5 0 5 0 T6 SBP_ACK input hold time 1 25 1 25 T1 T9 SBP_CLK I SBP_ACK I SBP_FRAME I O SBP_DATA 7 0 I O S...

Page 404: ...ts the pin numbers in sequence including pin name I O voltage and I O type and Figure 18 44 shows the pinout Note that some pin numbers are multiplexed and therefore have multiple pin names signal names T7 SBP_FRAME input setup time 5 0 5 0 T8 SBP_FRAME input hold time 1 25 1 25 T9 SBP_REQ output hold time 3 0 4 0 T10 SBP_RD output hold time 3 0 4 0 T11 SBP_DATA output hold time 3 0 4 0 T12 SBP_DA...

Page 405: ...CT I A4 NC NO CONNECT I A5 VI_CLK 0 3 3 5 I A6 NC NO CONNECT I A7 PLL_BYPASS 3 3 I A8 VSS_A GROUND A9 VSS_A GROUND A10 CLKI 3 3 I A11 XVDD 3 3 O A12 CLKO 3 3 O A13 AI_MCLKO 3 3 O A14 AO_SCLK 3 3 O A15 AO_D 3 3 3 O A16 SDRAM_WE 2 5 3 3 O A17 SDRAM_A 2 2 5 3 3 O A18 SDRAM_A 15 2 5 3 3 O A19 SDRAM_A 0 2 5 3 3 O A20 SDRAM_A 5 2 5 3 3 O B1 NC NO CONNECT I B2 VI_D 2 3 3 5 I B3 VI_D 7 3 3 5 I B4 NC NO CO...

Page 406: ...3 I O B13 AO_MCLKO 3 3 O B14 AO_IEC958 3 3 O B15 AO_D 2 3 3 O B16 SDRAM_RAS 2 5 3 3 O B17 SDRAM_CAS 2 5 3 3 O B18 SDRAM_A 4 2 5 3 3 O B19 SDRAM_A 1 2 5 3 3 O B20 SDRAM_A 7 2 5 3 3 O C1 VI_VSYNC 0 3 3 5 I C2 VI_D 4 3 3 5 I C3 VI_D 3 3 3 5 I C4 VI_D 6 3 3 5 I C5 NC NO CONNECT I C6 NC NO CONNECT I C7 TDI 3 3 I C8 VSS_A GROUND C9 VSS_A GROUND C10 VSS_X GROUND Table 18 34 DMN 8600 Pin List Cont Number ...

Page 407: ..._2 5 2 5 3 3 C17 SDRAM_A 3 2 5 3 3 O C18 SDRAM_A 6 2 5 3 3 O C19 SDRAM_A 10 2 5 3 3 O C20 SDRAM_A 14 2 5 3 3 O D1 VO_D 13 3 3 O D2 NC NO CONNECT I D3 VI_D 5 3 3 5 I D4 VDD_1 8 1 8 D5 VDD_3 3 3 3 D6 NC NO CONNECT I D7 TRST 3 3 I D8 TCK 3 3 I D9 VDD_A 3 3 D10 VDD_A 3 3 D11 VDD_RREF 3 3 D12 AI_D 1 3 3 I D13 AO_FSYNC 3 3 O D14 AO_D 0 3 3 O D15 VDD_2 5 2 5 3 3 Table 18 34 DMN 8600 Pin List Cont Number ...

Page 408: ... 3 3 O E2 VO_D 12 3 3 O E3 VO_D 14 3 3 O E4 VDD_3 3 3 3 E9 VDD_3 3 3 3 E10 VDD_1 8 1 8 E11 VDD_3 3 3 3 E12 VDD_1 8 1 8 E17 SDRAM_A 12 2 5 3 3 O E18 SDRAM_A 13 2 5 3 3 O E19 SDRAM_DQ 25 2 5 3 3 I O E20 SDRAM_DQS 3 For DDR parts only 2 5 3 3 I O F1 VO_D 7 3 3 O F2 VO_D 8 3 3 O F3 VO_D 11 3 3 O F4 VO_D 15 3 3 O F17 SDRAM_A 11 2 5 3 3 O F18 SDRAM_DQ 26 2 5 3 3 I O F19 SDRAM_DQ 30 2 5 3 3 I O Table 18 ...

Page 409: ... 5 3 3 I O G19 SDRAM_DQM 3 2 5 3 3 O G20 SDRAM_CLK 1 2 5 3 3 O H1 VO_CLK 3 3 I O H2 VO_D 1 3 3 O H3 VO_D 2 3 3 O H4 VO_D 3 3 3 O H8 VSS GND H9 VSS GND H10 VSS GND H11 VSS GND H12 VSS GND H13 VSS GND H17 SDRAM_DQ 29 2 5 3 3 I O H18 SDRAM_DQ 22 2 5 3 3 I O H19 SDRAM_DQ 23 2 5 3 3 I O H20 SDRAM_CLK 1 For DDR parts only 2 5 3 3 O J1 BIO_PHY_DATA 4 3 3 I O J2 BIO_PHY_DATA 0 3 3 I O Table 18 34 DMN 8600...

Page 410: ...VSS GND J16 VDD_2 5 2 5 3 3 J17 SDRAM_DQ 21 2 5 3 3 I O J18 SDRAM_DQ 20 2 5 3 3 I O J19 SDRAM_DQS 2 For DDR parts only 2 5 3 3 I O J20 SDRAM_DQ 19 2 5 3 3 I O K1 BIO_PHY_DATA 5 3 3 I O K2 BIO_PHY_DATA 6 3 3 I O K3 BIO_PHY_DATA 7 3 3 I O K4 BIO_LINK_ON 3 3 I K5 VDD_3 3 3 3 K8 VSS GROUND K9 VSS GROUND K10 VSS GROUND K11 VSS GROUND K12 VSS GROUND K13 VSS GROUND Table 18 34 DMN 8600 Pin List Cont Numb...

Page 411: ..._PHY_CTL 1 3 3 I O L3 BIO_PHY_DATA 1 3 3 I O L4 BIO_LPS 3 3 O L5 VDD_3 3 3 3 L8 VSS GROUND L9 VSS GROUND L10 VSS GROUND L11 VSS GROUND L12 VSS GROUND L13 VSS GROUND L16 VDD_2 5 2 5 3 3 L17 SDRAM_DQM 1 2 5 3 3 O L18 SDRAM_DQ 8 2 5 3 3 I O L19 SDRAM_DQ 11 2 5 3 3 I O L20 SDRAM_DQ 13 2 5 3 3 I O M1 BIO_LREQ 3 3 O M2 BIO_PHY_DATA 3 3 3 I O M3 BIO_PHY_DATA 2 3 3 I O M4 ATAPI_DATA 8 SBP_DATA 0 3 3 5 I O...

Page 412: ...Q 12 2 5 3 3 I O M18 SDRAM_DQ 14 2 5 3 3 I O M19 SDRAM_DQS 1 For DDR parts only 2 5 3 3 I O M20 SDRAM_DQ 10 2 5 3 3 I O N1 ATAPI_DATA 7 SD_DATA 7 3 3 5 I O N2 ATAPI_DATA 6 SD_DATA 6 3 3 5 I O N3 ATAPI_DATA 9 SBP_DATA 1 3 3 5 I O N4 ATAPI_DATA 5 SD_DATA 5 3 3 5 I O N8 VSS GROUND N9 VSS GROUND N10 VSS GROUND N11 VSS GROUND N12 VSS GROUND N13 VSS GROUND N17 SDRAM_DQM 0 2 5 3 3 O Table 18 34 DMN 8600 ...

Page 413: ...TA 3 CD_C2PO 3 3 5 I O P4 ATAPI_DATA 2 SD_DATA 2 CD_BCK 3 3 5 I O P17 SDRAM_DQ 4 2 5 3 3 I O P18 SDRAM_DQ 6 2 5 3 3 I O P19 SDRAM_DQ 7 2 5 3 3 I O P20 SDRAM_CLK 0 2 5 3 3 O R1 ATAPI_DATA 11 SBP_DATA 3 3 3 5 I O R2 ATAPI_DATA 12 SBP_DATA 4 3 3 5 I O R3 ATAPI_DATA 1 SD_DATA 1 CD_LRCK 3 3 5 I O R4 ATAPI_DATA 0 SD_DATA 0 CD_DATA 3 3 5 I O R17 SDRAM_DQ 0 2 5 3 3 I O R18 SDRAM_DQ 2 2 5 3 3 I O R19 SDRAM...

Page 414: ... 8 1 8 T11 VDD_3 3 3 3 T12 VDD_3 3 3 3 T17 VSS_DLL GROUND T18 SIO_SPI_MISO M_A 1 3 3 5 3 3 I O T19 SDRAM_DQ 1 2 5 3 3 I O T20 SDRAM_DQ 3 2 5 3 3 I O U1 ATAPI_DMAACK SD_SECSTART 3 3 3 3 5 O I O U2 ATAPI_DATA 14 SBP_DATA 6 3 3 5 I O U3 ATAPI_ADDR 3 SBP_REQ 3 3 O U4 VDD_1 8 1 8 U5 VDD_5 5 U6 H_DATA 23 M_A 24 3 3 5 3 3 I O O U7 H_INT M_GPIO 0 3 3 3 3 5 op dr O I O U8 H_RD WR M_RD WR 3 3 5 3 3 I O Tabl...

Page 415: ...I O U13 M_ALE 3 3 O U14 SIO_IRTX1 M_A 2 3 3 O U15 VDD_DLL 1 8 U16 VDD_DLL 1 8 U17 VSS_DLL GROUND U18 SIO_SPI_MOSI M_A 25 3 3 O U19 SIO_UART2_TX 3 3 O U20 SIO_UART1_TX M_A 4 3 3 O V1 ATAPI_ADDR 2 SBP_RD 3 3 O V2 ATAPI_ADDR 1 SBP_ACK 3 3 3 3 5 O I V3 ATAPI_DIOR SD_RDREQ 3 3 O V4 ATAPI_ADDR 4 SBP_CLK 3 3 3 3 5 O I V5 H_DATA 29 M_CS 3 3 3 5 3 3 I O O V6 H_DATA 26 M_CS 0 3 3 5 3 3 I O O Table 18 34 DMN...

Page 416: ...9 M_D 13 3 3 5 I O V12 H_DATA 10 M_A 16 M_D 10 3 3 5 I O V13 H_DATA 7 M_A 13 M_D 7 3 3 5 I O V14 H_DATA 3 M_A 9 M_D 3 3 3 5 I O V15 H_DMAREQ M_UWE UDS 3 3 O V16 SIO_SPI_CS 2 M_A 22 3 3 O V17 SIO_UART1_CTS M_RD WR 3 3 I O V18 SIO_SPI_CS 1 M_A 23 3 3 O V19 SIO_SCL 3 3 5 I O V20 SIO_UART1_RTS M_A 3 3 3 O W1 ATAPI_DMARQ SD_ERROR 3 3 5 I W2 ATAPI_INTRQ SD_ACK 3 3 5 I W3 ATAPI_ADDR 0 SBP_FRAME 3 3 3 3 5...

Page 417: ...5 3 3 I O O W9 H_ADDR 2 M_GPIO 3 3 3 5 3 3 5 I I O W10 H_ADDR 1 M_GPIO 2 3 3 5 3 3 5 I I O W11 H_DATA 9 M_A 15 M_D 9 3 3 5 I O W12 H_DATA 6 M_A 12 M_D 6 3 3 5 I O W13 H_DATA 2 M_A 8 M_D 2 3 3 5 I O W14 H_DATA 1 M_A 7 M_D 1 3 3 5 I O W15 H_DATA 0 M_A 6 M_D 0 3 3 5 I O W16 H_RST M_RST 3 3 5 I W17 SIO_IRTX2 M_OE 3 3 O W18 SIO_SPI_CS 3 M_A 5 3 3 O W19 SIO_UART1_RX M_CS 0 3 3 I O W20 SIO_UART2_RX 3 3 5...

Page 418: ... Y6 H_DATA 24 M_A 25 3 3 5 3 3 I O O Y7 H_DATA 18 M_A 3 3 3 5 3 3 I O O Y8 H_DATA 19 M_A 4 3 3 5 3 3 I O O Y9 H_CS M_GPIO 5 3 3 5 3 3 5 I I O Y10 H_RD M_GPIO 4 3 3 5 3 3 5 I I O Y11 H_DATA 15 M_A 21 M_D 15 3 3 5 I O Y12 H_DATA 11 M_A 17 M_D 11 3 3 5 I O Y13 H_ADDR 0 M_GPIO 1 3 3 5 3 3 5 I I O Y14 H_DATA 4 M_A 10 M_D 4 3 3 5 I O Y15 M_OE 3 3 O Y16 MCONFIG 1 3 3 5 I Y17 SIO_SPI_CLK M_A 26 3 3 3 3 O ...

Page 419: ...oltage applied to the VDD pins associated with them Y18 SIO_SDA 3 3 5 I O Y19 SIO_SPI_CS 0 M_A 24 3 3 O Y20 SIO_IRRX 3 3 5 I 1 For input pins voltage means tolerance for output pins voltage means output drive level 2 DDR refers to Double Data Rate SDRAMs which have double the bandwidth of standard SDRAMs and are used for high performance non power critical applications Table 18 34 DMN 8600 Pin Lis...

Page 420: ... VDD_RREF VDD_3 3 VSS VSS VSS A12 B12 C12 D12 E12 H12 J12 K12 CLKO AI_SCLK AI_FSYNC AI_D 1 VDD_3 3 VSS VSS VSS A13 B13 C13 D13 H13 J13 K13 AI_MCLKO AO_MCLKO AI_D 0 AO_FSYNC VSS VSS VSS A14 B14 C14 D14 AO_SCLK AO_IEC958 AO_D 1 AO_D 0 A15 B15 C15 D15 AO_D 3 AO_D 2 SDRAM_CKE VDD_2 5 A16 B16 C16 D16 J16 K16 SDRAM_WE SDRAM_RAS VDD_2 5 SDRAM_ VREF1 1 For DDR parts only DDR refers to Double Data Rate SDR...

Page 421: ..._DATA 19 M_A 4 K9 M9 N9 T9 U9 V9 W9 Y9 VSS VSS VSS VDD_1 8 H_DTACK M_DTACK H_WAIT M_WAIT H_DATA 16 M_A 1 H_CS M_GPIO 5 L10 M10 N10 T10 U10 V10 W10 Y10 VSS VSS VSS VDD_1 8 H_DATA 14 M_A 20 M_D 14 H_DATA 12 M_A 18 M_D 12 H_ADDR 1 M_GPIO 2 H_RD M_GPIO 4 L11 M11 N11 T11 U11 V11 W11 Y11 VSS VSS VSS VDD_3 3 H_DATA 8 M_A 14 M_D 8 H_DATA 13 M_A 19 M_D 13 H_DATA 9 M_A 15 M_D 9 H_DATA 15 M_A 21 M_D 15 L12 M...

Page 422: ...Y_ DATA 1 L3 BIO_PHY_ DATA 2 M3 BIO_PHY_ DATA 3 M2 BIO_PHY_ DATA 4 J1 BIO_PHY_ DATA 5 K1 BIO_PHY_ DATA 6 K2 BIO_PHY_ DATA 7 K3 CLKI A10 CLKO A12 CLKX B10 H_ADDR 0 M_GPIO 1 Y13 H_ADDR 1 M_GPIO 2 W10 H_ADDR 2 M_GPIO 3 W9 H_CS M_GPIO 5 Y9 H_DATA 0 M_A 6 M_D 0 W15 H_DATA 10 M_A 16 M_D 10 V12 H_DATA 11 M_A 17 M_D 11 Y12 H_DATA 12 M_A 18 M_D 12 V10 H_DATA 13 M_A 19 M_D 13 V11 H_DATA 14 M_A 20 M_D 14 U10...

Page 423: ... J13 VSS K8 VSS K9 VSS K10 VSS K11 VSS K12 VSS K13 VSS L8 VSS L9 VSS L10 VSS L11 VSS L12 VSS L13 VSS M8 VSS M9 VSS M10 VSS M11 VSS M12 VSS M13 VSS N8 VSS N9 VSS N10 VSS N11 VSS N12 VSS N13 VSS_2 5 K16 VSS_A A8 VSS_A A9 VSS_A C8 VSS_A C9 VSS_DLL T17 VSS_DLL U17 VSS_RREF B11 VSS_X C10 XVDD A11 VDD_3 3 K5 VDD_3 3 L5 VDD_3 3 T4 VDD_3 3 T11 VDD_3 3 T12 VDD_5 U5 VDD_A B8 VDD_A B9 VDD_A D9 VDD_A D10 VDD_...

Page 424: ...l rights reserved 18 4 Package Mechanical Specifications This section provides the dimensions and recommended manufacturing conditions for the DMN 8600 processor 18 4 1 Package Dimensions The DMN 8600 processor is available in a 308 pin ball grid array BGA package illustrated in Figure 18 45 ...

Page 425: ...6 0 048 b 0 75 0 030 c 0 51 0 56 0 61 0 020 0 022 0 024 D 26 80 27 00 27 20 1 055 1 063 1 071 D1 24 13 0 950 D2 23 80 24 00 24 20 0 937 0 945 0 953 D3 17 95 18 00 18 05 0 707 0 709 0 711 E 26 80 27 00 27 20 1 055 1 063 1 071 E1 24 13 0 950 E2 23 80 24 00 24 20 0 937 0 945 0 953 E3 17 95 18 00 18 05 0 707 0 709 0 711 e 1 27 0 050 ddd 0 15 0 006 q 30 Typ 30 Typ 1 The metric millimeter values are the...

Page 426: ...ce may occur during ultrasonic washing based on the frequency and PCB shape This resonance might affect ball strength Table 18 36 specifies the recommended hot air or infrared IR solder reflow conditions Table 18 36 Recommended Hot Air or IR Solder Reflow Conditions Parameter Specification Preheating Temperature 140 to 160 C Preheating Temperature Hold Time 60 to 120 s Heating Acceleration 1 to 3 ...

Page 427: ...ster 14 5 External DRAM Configuration Register 13 10 GPIO Value Register 10 17 Host Address Register 32 Bit Mode 8 21 Host Address Register for LE 0 in 16 Bit Mode 8 21 Host Address Register for LE 1 in 16 Bit Mode 8 21 Host Control Register 8 12 Host Data Register 16 Bit Mode for LE 0 8 19 Host Data Register 16 Bit Mode for LE 1 8 19 Host Data Register 32 Bit Mode 8 19 Host DMA Configuration Regi...

Page 428: ... Address Pointer1 Register IR_RX_ADDR_PTR1_ADDR 15 61 IR1 DMA Receive Address Pointer2 Register IR_RX_ADDR_PTR2_ADDR 15 61 IR1 DMA Receive Address Pointer3 Register IR_RX_ADDR_PTR3_ADDR 15 62 IR1 DMA Receive Address Pointer4 Register IR_RX_ADDR_PTR4_ADDR 15 62 IR1 DMA Receive Control Register IR_RX_CONTROL_REG_ADDR 15 59 IR1 DMA Receive Status Register IR_RX_STATUS_REG_ADDR 15 60 IR1 DMA Transmit ...

Page 429: ...stream Configuration Register 9 8 SIO DMA Engine Interrupt Mask Register INTR_MASK_ADDR 15 21 SIO DMA Engine Interrupt Status Register INTR_STATUS_ADDR 15 22 SIO DMA Engine Priority Selection Register PRI_SEL_ADDR 15 24 SIO Top Level DMA Interrupt Mask Register SIO_DMA_MASK 15 31 SIO Top Level DMA Interrupt Status Register SIO_DMA_IRQ 15 28 SIO Top Level Module Interrupt Enable Register SIO_IRQ_EN...

Page 430: ...ceive Address Pointer2 Register UART1_RX_ADDR_PTR2_ADDR 15 102 UART1 DMA Receive Address Pointer3 Register UART1_RX_ADDR_PTR3_ADDR 15 103 UART1 DMA Receive Address Pointer4 UART1_RX_ADDR_PTR4_ADDR 15 103 UART1 DMA Receive Control Register UART1_RX_CONTROL_REG_ADDR 15 100 UART1 DMA Receive Status Register UART1_RX_STATUS_REG_ADDR 15 101 UART1 DMA Transmit Address Pointer1 Register UART1_TX_ADDR_PTR...

Page 431: ...ess Pointer2 Register UART2_TX_ADDR_PTR2_ADDR 15 98 UART2 DMA Transmit Address Pointer3 Register UART2_TX_ADDR_PTR3_ADDR 15 98 UART2 DMA Transmit Address Pointer4 Register UART2_TX_ADDR_PTR4_ADDR 15 99 UART2 DMA Transmit Control Register UART2_TX_CONTROL_REG_ADDR 15 95 UART2 DMA Transmit Status Register UART2_TX_STATUS_REG_ADDR 15 97 UART2 External Clock Prescaler Register UART2_PRESCALER 15 94 UA...

Page 432: ...l A 6 Register Listing Copyright 2001 2002 by LSI Logic Corporation All rights reserved Video Output Clock Control Register 16 6 Video Overlay Control Register 11 20 Video Status Register 11 15 Wake Up Source Register 16 11 ...

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