LSI Logic Confidential
SIO Register Descriptions
15-39
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
master write, not the data requested by the winning master.
This caution applies only in a multi-master environment.
IDC Clock Register (IDC_CLOCK)
Offset = 0xBE0098
Read/Write
Default = 0x007D 0000
IDCSCL
IDC Clock Frequency
[25:16]
This field sets an upper bound on the IDC clock fre-
quency. This upper bound is given by (sysclk / 4*IDC-
SCL). The actual IDC clock frequency is also affected by
the amount of filtering applied by the IDC Receive Filter
register. Since this filtering internally delays the rising
edges of the SIO_SCL line, it effectively slows down the
bus. With filtering employed, the IDC clock frequency is
on the order of:
frequency = sysclk / [(4*IDCSCL) + (1)(1)]
IDC FIFO Fullness Register (IDC_FIFO_STATUS)
Offset = 0xBE009C
Read Only
Default = 0x0000 0000
Byte2Rd
Bytes To Read
[27:24]
The actual number of bytes left to receive in master
receive mode.
RxCNT
Received Byte Count
[23:20]
Number of bytes in (“fullness” of) the received data FIFO.
31
26
25
16
Reserved
IDCSCL
15
0
Reserved
31
28
27
24
23
20
19
16
Reserved
Byte2Rd
RxCNT
TxCNT
15
0
Reserved