LSI Logic Confidential
6-15
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
ATAPI_DMARQ
W1
I
Device DMA request. This pin is shared with
SD_ERROR.
ATAPI_DMAACK
U1
O
ATAPI DMA acknowledgement. This pin is shared
with SD_SECSTART.
SBP Interface
As Bitstream I/O pins, SBP signals are shared with up to two other signals per pin. One of these three
possible configurations is selected by MCONFIG[2:0] and the DVD control register (see description of
DVD control register on
SBP_DATA[7:0]
Y2, U2, T2, R2,
R1, P2, N3, M4
I
SBP data bus. Multiplexed with ATAPI_DATA[15:8]
only during non-ATAPI mode.
SBP_CLK
V4
I
SBP clock. All signals are sampled and driven on
the rising edge.
SBP_REQ
U3
O
SBP request for data transfer (WrReq = 0) or write
transfer request (WrReq = 1). Active low if POL = 1,
otherwise active high.
SBP_RD
V1
O
SBP read/write transfer (WrReq = 0) or read transfer
request (WrReq = 1). Active low if POL = 1 and
WrReq = 1, otherwise active high.
SBP_ACK
V2
I
Transfer of data acknowledged by system. Active
low if POL = 1, otherwise active high.
SBP_FRAME
W3
I/O
Indicates first byte of each frame.
SPI (Serial I/O)
As Serial I/O pins, SIO_SPI pins are shared with up to one other signal per pin. MCONFIG[1:0] = 00
selects the SIO_SPI signals listed below.
SIO_SPI_CLK
Y17
O
SPI clock. Multiplexed with M_A[26].
SIO_SPI_MOSI
U18
O
SPI master out slave in. Multiplexed with M_A[25].
SIO_SPI_MISO
T18
I
SPI master in slave out. Multiplexed with M_A[1].
SIO_SPI_CS[3:0]
W18, V16, V18,
Y19
O
SPI chip selects. Multiplexed with M_A[24:22],
M_A[5].
Table 6.1
DMN-8600 Pin Descriptions (Cont.)
Name
Pin No.
Type
1
Description