LSI Logic Confidential
SIO Register Descriptions
15-87
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
UART1 FIFO Control Register (FCR)
Offset = 0xBE0108 / 0xBE0188
Write only
Default = 0x0000 0000
FCR[7:6]
Trigger Level
31:30
These bits are used to set the trigger levels for the
receive FIFO interrupt, as shown in
FCR[3]
Mode Control / DMA Enable
27
1= The internal UART signals nrxrdy and ntxrdy change
from mode 0 to mode1 if FCR[0]=1. This bit must be set
high if the user wishes to use the DMA Engine to
feed/drain the UARTs with data.
FCR[2]
Clear Transmit FIFO
26
1 = Clear all bytes in the transmit FIFO and reset its
counter to 0. The shift register is not cleared. The 1 that
is written to this bit is self-clearing.
FCR[1]
Clear Receive FIFO
25
1 = Clear all bytes in the receive FIFO and resets its
counter to 0. The shift register is not cleared. The 1 that
is written to this bit is self-clearing.
FCR[0]
Enable FIFOs
24
1= Enable both the transmit and receive FIFOs.
0 = Clear all bytes in both FIFOs.
31
30
29
28
27
26
25
24
23
16
FCR7
FCR6
RSVD
FCR3 FCR2 FCR1 FCR0
RSVD
15
0
RSVD
Table 15.12 FCR Trigger Levels
FCR7
FCR6
Interrupt Type
0
0
Trigger Level = 01 (default)
0
1
Trigger Level = 04
1
0
Trigger Level = 08
1
1
Trigger Level = 14