DMN-8600 DVD Recorder System Processor
10-1
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
LSI Logic Confidential
Chapter 10
Host Async Master
Interface
This chapter describes the host async master interface and contains the
following sections:
•
•
Section 10.2, “Host (Slave) plus Limited Master”
•
Section 10.3, “Master Replaces Slave”
•
•
Section 10.5, “Chip Select Configuration Registers”
•
Section 10.6, “Interrupt/GPIO Configuration and Value Registers”
•
Section 10.7, “Async Master Status/Time-Out Register”
•
Section 10.8, “Async Master SPARC Error Address Register”
The DMN-8600 async master interface has three pin configurations,
described below, to optimize the total pin-count for different package and
system configurations. One of three configurations is selected by the
MCONFIG[1:0] pins. The configuration pins must not change after reset.
10.1 No Master
In this configuration (MCONFIG = 00), the master interface is not used.
The master space is swapped with the DRAM space in the SPARC
address map, changing the start of SDRAM to zero. The SCPU rst bit
will remain set after reset to allow the host processor to download
microcode before booting.