LSI Logic Confidential
SIO Register Descriptions
15-73
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
FLUS
FIFO Flush
1
This is a self-clearing bit for flushing the DMA channel’s
two internal FIFOs.
For transmit channels, when FLUS is set, all data cur-
rently in the channel FIFOs is dropped.
For receive channels, all data currently in the channel
FIFOs is sent to the SDRAM address indicated by
ADDR_PTR3.
Setting FLUS does not terminate a transfer; it merely
dumps data (if transmit) or sends whatever data remains
in the FIFOs up to the SDRAM (if receive).
CHEN
DMA Channel Enable
0
This bit enables/disables the DMA channel. If CHEN is
cleared during a DMA operation, DMA is paused. Set
CHEN again to resume the DMA operation. All state
information is preserved when DMA is paused, and the
DMA operation continues from where it left off.
CHEN is controlled by software. It must be cleared once
the DMA operation has finished. On reset, CHEN is 0.
SPI DMA Transmit Status Register (SPI_TX_STATUS_REG_ADDR)
Offset = 0xBE0044
Read/Write
Default = 0x0000 0000
FLSTS
FIFO Flush Status
19
1 = Flushing of a particular DMA channel is complete.
Software must reset FLSTS by writing 0.
FLVLB
FIFO B Byte Count
18:10
This field shows the number of bytes currently held in
FIFO B.
FLVLA
FIFO A Byte Count
9:1
This field shows the number of bytes currently held in
FIFO A.
31
20
19
18
16
RSVD
FLSTS
FLVLB
15
10
9
1
0
FLVLB
FLVLA
CHST