LSI Logic Confidential
18-24
Specifications
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
should be used as the sampling edge for the data on SDRAM_DQ. DQS
is generally placed in the center of the valid data window.
Figure 18.19 DMN-8600 Write to SDRAM in DDR Mode
Please note the following related information:
•
Control pins include SDRAM_CAS, SDRAM_RAS, SDRAM_WE, and
address pins include SDRAM_A[15:0], all of which are outputs of
DoMiNo
•
SDRAM_DQ[31:0] and SDRAM_DQS[3:0] are driven from
DMN-8600 for writes to SDRAM.
T
2
T
1
SDRAM_CLK (O)
SDRAM_CLK (O)
SDRAM_DQS[3:0] (I/O)
Control/Addr Pins (O)
SDRAM_DQ[31:0] (I/O)
T
3
T
4
T
4
T
5
T
5
Table 18.14 DMN-8600 Write to SDRAM (DDR Mode) Parameters
Symbol
Description
Min
Max
Unit
T
1
Control/Addr pins output delay
4.5
ns
T
2
Control/Addr pins hold time
1.0
ns
T
3
Output data strobe delay
0.75
1.25
T
CYC
T
4
Output data setup time
1.5
ns
T
5
Output data hold time
1.0
ns