LSI Logic Confidential
15-66
Serial I/O Port
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Figure 15.10 SPI Inter-Byte Blanking
CSBK
SPI Chip Select Blanking Level
9
1 = SIO_SPI_CS[n] is negated during the inter-byte
blanking period.
IBBM
Inter-Byte Blanking Mode
8
1 = Inter-byte blanking is allowed between the first and
second bytes only.
0 = Inter-byte blanking is allowed between every byte.
LSBF
Least Significant Bit First
7
1 = The least significant bit of each write byte is shifted
out first, and each read byte in the SPI_SHIFT register is
swapped before writing it to the SPI_TEMP register.
Since the swapping occurs between the SPI_SHIFT reg-
ister and the data registers, software must shift bits for
bytes in the SPI_SHIFT register.
0 = The most significant bit of each write byte is shifted
out first.
CSDL[2:0]
SPI Chip Select Delay
6:4
These bits allow adjustment of the setup and hold times
of the SIO_SPI_CS[n] about SPI_CLK. CSDL is the num-
ber of half SIO_SPI_CLK cycles between the following
events:
CSDL
SPACE
CSDL
CS_OFF
0
1
2
3
4
5
6
7
SPICS
SPICLK
WHERE:
CSBK
CSDL
IBBK
SPACE
CS_OFF
NOTES
x
x
0
1
0
0
n>0
n>0
0
1
m>0
m>0
(2*CSDL)+IBBK
(2*CSDL)+IBBK IBBK
General Case
General Case