LSI Logic Confidential
AC Timing
18-23
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
A read command is issued to read data from SDRAM. DRAM returns
data on the 2nd/3rd cycle after the command, depending on the CAS
latency.
Figure 18.18 DMN-8600 Reading from SDRAM in SDR Mode
Please note the following related information:
•
Control pins include SDRAM_CAS, SDRAM_RAS, SDRAM_WE, and
address pins include SDRAM_A[15:0], all of which are outputs of
DoMiNo
•
SDRAM_DQ[31:0] is driven from the external DRAM chip.
•
A clock (with programmable phase shift) is utilized to capture the
input data on SDRAM_DQ. So, the value of T3 can be negative–that
is, data can appear on the cycle after the one indicated by the CAS
latency value. The internal programmable clock will be able to
capture the data up to the specified delay.
18.2.4.4
DMN-8600 Writing to SDRAM in DDR Mode
For DDR mode, when writing into the SDRAM, DMN-8600 drives
SDRAM_DQS signals together with the SDRAM_DQ pin. SDRAM_DQS
T
2
T
1
SDRAM_CLK (O)
Control/Addr Pins (O)
SDRAM_DQ[31:0] (I/O)
T
3
T
4
Table 18.13 DMN-8600 Read from SDRAM (SDR Mode) Parameters
Symbol
Description
Min
Max
Unit
T1
Control/Addr pins output delay
4.5
ns
T2
Control/Addr pins hold time
1.0
ns
T3
Input data setup time
2.0
ns
T4
Input data hold time
1.0
ns