LSI Logic Confidential
8-16
Host Slave Interface
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
1 = Reset RISC core and DSP.
0 = Normal operation.
Crst
Chip Reset
1
This writable, self-clearing bit resets the DMN-8600 chip,
except for portions of the Host interface, with all affected
units are left in a quiescent state.
This bit is also set by driving the external RST signal
active, and is held until RST is released.
The contents of the SDRAM are undefined after setting
ChipRst. (Use CPURst instead to inspect the SDRAM.)
1 = Reset processor chip.
0 = Normal operation.
WrD
0
The value of this bit is written in the Host Control
Register. The field that needs to be written is indicated by
a logic value 1 in that bit position. A logic value 0 in that
bit position indicates that the field is not updated.
Value to write to other Host Control Register bit fields.
8.6.2
Version Register
This 16-bit register indicates the silicon chip version number. The version
is in the most-significant eight bits, and stepping information is in the
least significant eight bits. It is accessible as a Host space register using
H_ADDR[2:0], or as a CBus register. The initial value is 0x0900.
Version Register
Address: 0x1 (Host space)
0x60044 (CBus)
15
8
7
0
Version
Stepping Information