LSI Logic Confidential
6-11
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
H_CS
Y9
I
Host chip select. This pin is shared with M_GPIO[5].
H_WAIT
V9
O
Wait signal to the host. This pin is shared with
M_WAIT.
H_DTACK
U9
O
Host data transfer acknowledge. This pin is shared
with M_DTACK.
Host Master Interface
The master interface shares all of its pins with the host (slave) interface and some of its pins with the
Serial I/O interface pins. The host interface shares its pins with the (Async) Master interface, allowing
up to two signals per pin, Slave or Master, with three possible configurations selected by
MCONFIG[1:0] as follows:
MCONFIG[1:0] = 00 = Async slave only
MCONFIG[1:0] = 01 = Async slave + Async master (no UART1, SPI, IRTX)
MCONFIG[1:0] = 10 = Async master only
When Async Host plus Async Master is selected, the low order address and control pins other than
M_ALE (M_A[10:1], M_CS[0], M_OE, M_RD/WR) replace the Bitstream I/O pins for UART1, SPI and
IR transmit (UART2, IR receive and IDC are still available). The limited master is primarily intended
to support an external PROM accessed independently of the host processor; consequently, it only
supports one chip select with self-paced cycles.
M_GPIO[5:0]
Y9, Y10, W9,
W10, Y13, U7
I/O
General purpose I/O [5:0]. These pins are shared
with H_CS, H_RD, H_ADDR[2:0], and H_INT,
respectively.
M_RST
W16
I
Master Reset signal. This signal is shared with
H_RST (slave).
M_CS[5:0]
M_CS[0]
W4, Y3, V5,
W5, Y4, V6
(master)
W19
(slave/master)
O
Master chip select [5:0] outputs. These pins are
shared with H_DATA[31:26] (slave) pins when in
master mode. M_CS[0] is shared with UART1_RX
when in slave/limited master mode.
M_A[26:22]
V6, Y5, Y6, U6,
W6 (master)
Y17, U18, Y19,
V18, V16,
(slave/master)
O
Master address [26:22]. These pins are shared with
H_DATA[25:21] (slave) pins when in master mode,
and are shared with SPI pins when in slave/limited
master mode.
M_A[21:6]/
M_D[15:0]
Y11, U10, V11,
V10, Y12, V12,
W11, U11, V13,
W12, U12, Y14,
V14, W13,
W14, W15
I/O
Master muxed address [21:6] and data [15:0]. These
pins are shared with H_DATA[15:0] (slave) pins.
Table 6.1
DMN-8600 Pin Descriptions (Cont.)
Name
Pin No.
Type
1
Description