LSI Logic Confidential
Audio Input Control Register
12-7
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
interleaved samples from each channel. Within each set,
channel zero is stored at the lowest address and channel
2ChCnt - 1 at the highest address. With frame formats
having two samples per frame, even channels
correspond to the left sample in each frame and odd
channels to the right sample in each frame. With FrForm
equal to one, input status is captured from all 8 audio
channels, independent of the ChCnt value.
AudInt
4
If set, an audio input stream DMA transfer completion
interrupt will be generated when an audio input DMA
transfer has been completed. Completion interrupts are
queued by the hardware, resulting in a separate interrupt
for each transfer, even if a second transfer completes
before the first interrupt is taken. When the interrupt is
taken, the count of outstanding interrupts is decremented
by one.
Res
Reserved
3
IQF
2
A read-only bit which is set when there are two
outstanding DMA transfers in the audio input stream 1
command queue. A transfer is loaded into the queue
each time the GoI bit is set by software. A command is
removed from the queue each time the transfer
completes. This bit can be used by software to poll for
when to load the next command. Polling is typically used
for short transfers (<10 microseconds) and interrupts are
used for longer transfers.
0
1
This bit must be programmed to 0.
GoI
0
Set by microcode to queue up an audio input DMA
transfer using the most recently stored values in the
Audio Input 1 DMA address and length registers. The
GOI bit remains set while there is at least one audio input
1 DMA transfer outstanding. When all audio input
outstanding transfers are done, the DMA will clear the bit,