LSI Logic Confidential
Host Interface Registers
8-17
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Host DMA Data Register
Host Space Address: 0x6
8.6.3
Host DMA Data Register
The Host DMA Data Register is used when the Host configures the
DMN-8600 processor as a DMA target to transfer bitstream data to and
from the DMN-8600 device. It is accessible only as a Host space register
at address 0x6 via H_ADDR[2:0].
This register is the DMA target for the bitstream interface when BSSEP
is cleared in the Host Configuration register.
The size of the DMA reads or writes are 16 bits if H32 is cleared and
32 bits if H32 is set.
Reads or writes to this register when the H_DMAREQ pin is not asserted
are ignored.
8.6.3.1
Reading the Host DMA Data Register
Reading this register when H_DMAREQ is asserted transfers 16 or 32
bits from the internal bitstream FIFO to the host DMA channel and
deasserts H_DMAREQ.
At the end of the read, if additional data is available in the bitstream
FIFO, H_DMAREQ is reasserted.
8.6.3.2
Writing to the Host DMA Data Register
Writing to this register when H_DMAREQ is asserted transfers 16 or
32 bits of data from the host DMA channel to the internal bitstream FIFO
and deasserts H_DMAREQ.
If additional space is available in the internal bitstream FIFO,
H_DMAREQ is reasserted.
If LE is set, then Host DMA transfers between SDRAM and the Host
DMA Data Register are byte swapped, otherwise they are not swapped.
31
0
Data [31:0]