LSI Logic Confidential
Clock and Power Registers
16-9
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Audio Output Clock Control Register
Cbus Address: 0xC20014
AoPLLSr
31
If unset, the Ain PLL uses the internal CLKI as reference
clock. If set, uses Video Input 1 Clock pin as reference
clock. After power up, it is reset to ‘0’
AoutSrc
30
If set, the internally generated master output clock with
the clock frequency specified by the Aout Master field is
used for IEC-958 output timing and internally derived
output bit clock and output frame clock timing. If clear,
then an external master output clock is used, as supplied
on the MOclockI pin. In either case, the internally
generated master audio clock is output on the MOclockO
pin. At reset, this bit set if the PLL_BYPASS pin is zero,
otherwise it is reset.
The internal audio input master clock operating frequency
is determined by N and P as follows
:
N is interpreted as a 3.24 bit fractional number. In
DoMiNo, N values are restricted so that 13.5 MHz *
(N + 1)/2 is within
±
100 ppm of one of the frequencies
shown below:
88.2 * 384 kHz
96 * 384 kHz
176.4 * 256 kHz
192 * 256 kHz
After reset, N is set to 4.0176 and P is set to 3.
N
[29:3]
See above. This field is reset to 0x404816F.
P
[2:0]
See above. This field is reset to 0x3.
31
30
29
3
2
0
AoPLLSr
AoutSrc
N
P
AudioInClock
13.5 MHz
N
1
+
2 P
1
+
(
)
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