LSI Logic Confidential
15-60
Serial I/O Port
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
CHEN
DMA Channel Enable
0
This bit enables/disables the DMA channel. If CHEN is
cleared during a DMA operation, DMA is paused. Set
CHEN again to resume the DMA operation. All state
information is preserved when DMA is paused, and the
DMA operation continues from where it left off.
CHEN is controlled by software. It must be cleared once
the DMA operation has finished. On reset, CHEN is 0.
IR1 DMA Receive Status Register (IR_RX_STATUS_REG_ADDR)
Offset = 0xBF0064
Read/Write
Default = 0x0000 0000
FLSTS
FIFO Flush Status
19
1 = Flushing of a particular DMA channel is complete.
Software must reset FLSTS by writing 0.
FLVLB
FIFO B Byte Count
18:10
This field shows the number of bytes currently held in
FIFO B.
FLVLA
FIFO A Byte Count
9:1
This field shows the number of bytes currently held in
FIFO A.
CHST
DMA Channel Status
0
1 = The DMA transfer operation has finished. CHST can
be cleared by writing 1 to it.
31
20
19
18
16
RSVD
FLSTS
FLVLB
15
10
9
1
0
FLVLB
FLVLA
CHST