LSI Logic Confidential
18-32
Specifications
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
18.2.9 Video Interface Timing
and
show the AC timing for the DMN-8600
device Video interface.
Figure 18.26 AC Timing for Video Input Stream at VI_CLK[0]
Table 18.20 UART Interface AC Timing
Symbol
Description
Value
T
1
, T
2
, T
3
, T
4
Minimum data valid time for signals on SIO_UART pins.
3 sysclk cycles
T
1
VI_CLK[0] (I)
VI_D[9:2] (I)
VI_VSYNC[0] (I)
70%
50%
30%
T
C
T
HIGH
T
LOW
T
2
T
3
T
4
Valid