IEEE-488 Reference
3-114
Sequence Event Register:
Bit B0 —
Not used.
Bit B1, Layer 1 (Lay1) —
Set bit indicates that instrument operation is in arm layer 1 (PTR),
or that operation has exited from arm layer 1 NTR).
Bit B2, Layer 2 (Lay2) —
Set bit indicates that instrument operation is in arm layer 2 (PTR),
or that operation has exited from arm layer 2 NTR).
Bits B12 through B14 —
Not used
Bit B15 —
Always zero.
3.21.2
:ENABle <NRf>
:STATus:MEASurement:ENABle <NRf>
Program Measurement Event Enable Register
:STATus:QUEStionable:ENABle <NRf>
Program Questionable Event Enable Register
:STATus:OPERation:ENABle <NRf>
Program Operation Event Enable Register
:STATus:OPERation:TRIGger:ENABle <NRf>
Program Trigger Event Enable Register
:STATus:OPERation:ARM:ENABle <NRf>
Program Arm Event Enable Register
:STATus:OPERation:ARM:SEQuence:ENABle <NRf>
Program Sequence Event Enable Register
Parameters
<NRf> = 0
Clear register
<NRf> = 128
Set bit B7
1
Set bit B0
256
Set bit B8
2
Set bit B1
512
Set bit B9
4 Set bit B2
1024
Set bit B10
8
Set bit B3
2048
Set bit B11
16 Set bit B4
4096
Set bit B12
32 Set bit B5
8192
Set bit B13
64 Set bit B6
16384
Set bit B14
65535
Set all bits
Query
:ENABle?
Query enable register
Description
These commands are used to set the contents of the event enable registers (see Figures 3-28
through 3-33). An :ENABle command is sent with the decimal equivalent of the binary value
that determines the desired state (0 or 1) of each bit in the appropriate register.
Each event enable register is used as a mask for events (see [:EVENt] for descriptions of events).
When a bit in an event enable register is cleared (0), the corresponding bit in the event register
is masked and thus, cannot set the corresponding summary bit of the next register set in the sta-
Figure 3-27
Sequence Event Register
Lay2
B14 - B3
B2
B1
B0
(2 )
2
4
(2 )
1
2
0/1
0/1
Bit Position
Event
Decimal Weighting
Value
Value : 1 = Event Bit Set
0 = Event Bit Cleared
Event : Lay1 = Layer 1
Lay2 = Layer 2
Lay1
B15
0
