IDT 89HPES12T3G2, Preliminary User'S Manual

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Notes
PES12T3G2 User Manual 8 - 1 January 28, 2013
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Chapter 8
Configuration Registers
Configuration Space Organization
Each software visible register in the PES12T3G2 is contained in the PCI configuration space of one of
the ports. Thus, there are no registers in the PES12T3G2 that cannot be accessed by the root. Each soft-
ware visible register in the PES12T3G2 has a system address. The system address is formed by adding the
PCI configuration space offset value of the register to the base address of the port in which it is located. The
system address is used for serial EEPROM register initialization and slave SMBus register accesses.
The base address for each PES12T3G2 port is listed in Table 8.1. The PCI configuration space offset
addresses for registers in the upstream port are listed in Table 8.2 while the PCI configuration space offset
addresses for registers in downstream ports are listed Table 8.3.
As shown in Figure 8.1, upstream and downstream ports share a similar PCI configuration space
register layout.
– The upstream port contains global switch control and status registers as well as test mode regis-
ters which are not present in the configuration space of downstream ports.
– Due the ability to generate MSIs as a result of hot-plug events, the downstream ports contain an
MSI capability structure which is not present in the upstream port.
Reading from an upstream port offset not defined in Table 8.2 or a downstream offset not defined in
Table 8.3 returns a value of zero. Writes to such an offset complete successfully but modify no data and
have no other effect.
Software visible configuration registers exist with one or more fields that perform a side-effect action
when written. These side-effect actions may affect the ability of the switch to respond with a completion. For
example, writing a one to the Hot Reset (HRST) bit in the Switch Control (SWCTL) register initiates a hot
reset of the entire switch. Other examples are the FRST bit in SWCTL, the Link-Disable (LDIS) and Link-
Retrain (LRET) bits in the PCI Express Link Control register, as well as the Full Link Retrain (FLRET) field
that in the PHY Link State 0 (PHYLSTATE0) register. A configuration write to such a register returns a
completion to the Root before the side-effect action is performed. This is implemented by delaying the side-
effect action by 1 ms following generation of the completion. Thus, if the completion is not accepted by the
upstream port link partner in this time interval, then the completion will be lost.
Base
Address
PCI Configuration Space
0x0000 Port 0 configuration space (upstream port)
0x2000 Port 2 configuration space (downstream port)
0x4000 Port 4 configuration space (downstream port)
Table 8.1 Base Addresses for Port Configuration Space Registers