IDT 89HPES12T3G2, Preliminary User'S Manual

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IDT Link Operation
PES12T3G2 User Manual 3 - 3 January 28, 2013
Notes
Dynamic upconfiguration and downconfiguration is done on a per-link basis, and does not result in the
link going into a DL_Down state. A link can be downconfigured down to x1. A link can be upconfigured up to
the negotiated link width set after a full link train. For example, a link that trained to a width of x2 after a full
link train cannot be upconfigured to a width above x2.
When a link is downconfigured to a smaller width, inactive lanes are kept in Electrical Idle with their
receiver terminations enabled. These lanes continue to be associated with the downconfigured port’s
LTSSM. In order for upconfiguration to occur successfully, both of the link components must support it.
Furthermore, the PCIe specification recommends that a link component not initiate downconfiguration
unless the link partner supports link upconfiguration, except for link reliability reasons.
The capability to upconfigure a link is transmitted among components using the in-band TS2 ordered
set. When downconfiguration or upconfiguration of the link width occurs, one of the components on the link
initiates the process, while the other component responds to the process. The PCIe specification indicates
that both of these capabilities are optional.
Software may be notified of link width re-configuration via the link bandwidth notification mechanism
described in the PCIe 2.0 specification. This mechanism is enabled by setting the Link Bandwidth Manage-
ment Interrupt Enable (LBWINTEN) bit in the PCIELCTL register of switch downstream ports. Software can
prevent a device from initiating link width re-configuration for reasons other than reliability by setting the
Hardware Autonomous Width Disable (HAWD) bit in the port’s Link Control Register (PCIELCTL). Note that
the HAWD bit does not prevent a device from re-configuring the link width in response to link partner
requests.
Dynamic Link Width Re-Configuration Support in the PES12T3G2
The PES12T3G2 supports dynamic link width upconfiguration and down-configuration in response to
link partner requests. The PES12T3G2 ports do not autonomously initiate link width upconfiguration and
downconfiguration of links. Therefore, the Hardware Autonomous Width Disable (HAWD) bit in the port’s
PCIELCTL register has no effect and is hardwired to 0x0. Additionally, the PES12T3G2 port’s never set the
‘Autonomous Change’ bit in the training sets exchanged with the link partner during link training. Still, a link
partner connected to a PES12T3G2 downstream port may autonomously change link width. When this
occurs, the PES12T3G2 downstream port sets the Link Autonomous Bandwidth Status (LABWSTS) bit in
the PCIELSTS register.
Link Speed Negotiation
Background
The PCIe 2.0 specification introduces support for 5.0 Gbps data rates per lane (a.k.a., Gen2), in addition
to the 2.5 Gbps data rates (a.k.a, Gen1) mandated in previous versions of the specification. The PCIe spec
indicates that Gen2 support is optional while Gen1 support is mandatory.
All lanes of a link must operate at the same data rate. During full link training (i.e., from the Detect state),
links initially operate at 2.5 Gbps. Once the PHY Link Training State Machine (LTSSM) on both components
of the link reach the L0 state, the link speed may be upgraded to 5.0 Gbps if this capability is advertised by
both components. The process of upgrading the link speed does not result in a DL_Down state.
A component advertises its supported speeds via the Data Rate Identifier bits in the TS1 and TS2
training sets transmitted to its link partner during link training. The PCIe spec permits a component to
change its supported speeds dynamically. It is allowed for a component to advertise supported link speeds
without necessarily changing the link speed, via the Recovery LTSSM state.
A component determines the supported speeds of its link partner by examining the Data Rate Identifier
bits in the TS1/TS2 training sets received during link training, specifically in the Configuration.Complete and
Recovery.RcvrCfg states. The latest advertisement received overrides any previously recorded value.