IDT 89HPES12T3G2, Preliminary User'S Manual

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IDT Link Operation
PES12T3G2 User Manual 3 - 8 January 28, 2013
Notes
Active State Power Management
The operation of Active State Power Management (ASPM) is orthogonal to power management. Once
enabled by the ASPM field in the PCI Express Link Control (PCIELCTL) register, ASPM link state transi-
tions are initiated by hardware without software involvement. The PES12T3G2 ASPM supports the required
L0s state as well as the optional L1 state.
The upstream switch port has the following L0s entry conditions.
– The receive lanes of all of the switch downstream ports which are not in a low power state (i.e.,
D3) and whose link is not down are in the L0s state.
– The switch has no TLPs to transmit on the upstream port or there are no available flow control
credits to transmit a TLP.
– There are no DLLPs pending for transmission on the upstream port.
The downstream switch ports have the following L0s entry conditions.
– The receive lanes of the switch upstream port are in the L0s state.
– The switch has no TLPs to transmit on the downstream port or there are no available flow control
credits to transmit a TLP.
– There are no DLLPs pending for transmission on the downstream port.
If the L1 Entry conditions are met and the link is in the L0 or L0s state, then the hardware will request a
transition to the L1 state from its link partner. Note that L1 entry requests are only made by the PES12T3G2
upstream port. If the link partner acknowledges the transition, then the L1 state is entered. Otherwise the
L0s state is entered.
– The upstream switch port will only request entry into the L1 state when all of the downstream ports
which are not in a low power state (i.e., D3) and whose link is not down are in the L1 state.
Link Status
Associated with each port is a Port Link Up (PxLINKUPN) status output and a Port Activity (PxAC-
TIVEN) status output. These outputs are provided on I/O expander 4. See section I/O Expanders on page
5-6 for the operation of the I/O expander and the mapping of these status outputs to I/O expander pins.
The PxLINKUPN and PxACTIVEN status outputs may be used to provide a visual indication of system
state and activity or for debug. The PxLINKUPN output is asserted when the PCIe data link layer is up (i.e.,
when the LTSSM is in the L0, L0s, L1 or recovery states). When the data link layer is down, this output is
negated.
The PxACTIVEN output is asserted whenever any TLP, other than a vendor defined message, is trans-
mitted or received on the corresponding port’s link. Whenever a PxACTIVEN output is asserted, it remains
asserted for at least 200 ms. Since an I/O expander output may change no more frequently than once every
40 ms, this translates into five I/O expander update periods.
De-emphasis Negotiation
The PCI Express 2.0 specification requires that components support the following levels of de-
emphasis, depending on the link data rate:
– 2.5 Gbps (Gen1): De-emphasis = -3.5dB
– 5.0 Gbps (Gen2): De-emphasis = -3.5dB or -6.0dB
When operating at 5.0 Gbps, the de-emphasis is selected by programming the Selectable De-emphasis
(SDE) field in the PCI Link Control 2 Register (PCIELCTL2). The chosen de-emphasis for the link is the
result of a negotiation between the components of the link. Both components must operate with the same
de-emphasis across all lanes of the link.