IDT 89HPES12T3G2, Preliminary User'S Manual

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IDT
PES12T3G2 User Manual 4 January 28, 2013
Notes
Use of Hypertext
In Chapter 8, Tables 8.2 and 8.3 contain register names and page numbers highlighted in blue under the
Register Definition column. In pdf files, users can jump from this source table directly to the registers by
clicking on the register name in the source table. Each register name in the table is linked directly to the
appropriate register in the register section of the chapter. To return to the source table after having jumped
to the register section, click on the same register name (in blue) in the register section.
Reference Documents
PCI Express Base Specification, Revision 1.1, PCI Special Interest Group.
PCI Power Management Interface Specification, Revision 1.1, PCI Special Interest Group.
PCI to PCI Bridge Architecture Specification, Revision 1.2, PCI Special Interest Group.
SMBus Specification, Revision 2.0.
Revision History
May 23, 2007: Initial publication of preliminaray user manual.
June 26, 2007: In Chapter 8, Configuration Registers, included only 3 registers with addresses in the
0x400-0x600 range. Updated Chapter 3, Link Operation.
July 11, 2007: Corrected AERUCS to AERUES in AERCTL register, Chapter 8. Added additional regis-
ters to Chapter 8 in the 0x400-0x600 range.
February 6, 2008: Added PMETOATIMER register to Chapter 8.
October 31, 2008: In Chapter 8, revised description L0SEL field in the PCIELCAP register and LDIS
field in the PCIELCTL register.
September 15, 2010: In Table 1.9, changed Buffer type for PCI Express from CML to PCIe differential
and changed reference clocks to HCSL
February 22, 2012: Added paragraph after Table 5.11 to explain use of DWord addresses.
January 28, 2013: In Figure 5.8, changed No-ack to Ack between DATALM and DATAUM.
Read and Write Clear RW1C Software can read and write to registers/bits with this attribute.
However, writing a value of zero to a bit with this attribute has no
effect. A RW1C bit can only be set to a value of 1 by a hardware
event. To clear a RW1C bit (i.e., change its value to zero) a value
of one must be written to the location. An RW1C bit is never
cleared by hardware.
Read and Write when
Unlocked RWL Software can read the register/bits with this attribute. Writing to
register/bits with this attribute will only cause the value to be modi-
fied if the REGUNLOCK bit in the SWCNTL register is set. When
the REGUNLOCK bit is cleared, writes are ignored and the regis-
ter/bits are effectively read-only
Write Transient WT The zero is always read from a bit/field of this type. Writing of a
one is used to quality the writing of other bits/fields in the same
register.
Zero Zero A zero register or bit must be written with a value of zero and
returns a value of zero when read.
Type Abbreviation Description
Table 2 Register Terminology (Part 2 of 2)