IDT 89HPES12T3G2, Preliminary User'S Manual

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IDT Configuration Registers
PES12T3G2 User Manual 8 - 6 January 28, 2013
Notes
Downstream Ports
0x404 DWord SWCTL SWCTL - Switch Control (0x404) on page 8-54
0x408 DWord HPCFGCTL
HPCFGCTL - Hot-Plug Configuration Control (0x408) on page 8-55
0x418 DWord GPIOFUNC
GPIOFUNC - General Purpose I/O Control Function (0x418) on page 8-
56
0x41C DWord GPIOCFG
GPIOCFG - General Purpose I/O Configuration (0x41C) on page 8-56
0x420 DWord GPIOD
GPIOD - General Purpose I/O Data (0x420) on page 8-57
0x424 DWord SMBUSSTS
SMBUSSTS - SMBus Status (0x424) on page 8-57
0x428 DWord SMBUSCTL
SMBUSCTL - SMBus Control (0x428) on page 8-58
0x42C DWord EEPROMINTF
EEPROMINTF - Serial EEPROM Interface (0x42C) on page 8-58
0x434 DWord IOEXPADDR0
IOEXPADDR0 - SMBus I/O Expander Address 0 (0x434) on page 8-59
0x438 DWord IOEXPADDR1
IOEXPADDR1 - SMBus I/O Expander Address 1 (0x438) on page 8-59
0x450 DWord GPECTL
GPECTL - General Purpose Event Control (0x450) on page 8-59
0x454 DWord GPESTS
GPESTS - General Purpose Event Status (0x454) on page 8-60
0x500 Dword P0_SERDESCTL SERDESCTL- SerDes Control (0x500) on page 8-60
0x534 Dword P0_PHYLSTATE0 PHYLSTATE0 - Phy Link State 0 (0x534) on page 8-61
Cfg.
Offset Size
Register
Mnemonic
Register Definition
0x000 Word Px_VID VID - Vendor Identification Register (0x000) on page 8-10
0x002 Word Px_DID DID - Device Identification Register (0x002) on page 8-10
0x004 Word Px_PCICMD PCICMD - PCI Command Register (0x004) on page 8-10
0x006 Word Px_PCISTS PCISTS - PCI Status Register (0x006) on page 8-11
0x008 Byte Px_RID RID - Revision Identification Register (0x008) on page 8-12
0x009 3 Bytes Px_CCODE CCODE - Class Code Register (0x009) on page 8-12
0x00C Byte Px_CLS CLS - Cache Line Size Register (0x00C) on page 8-12
0x00D Byte Px_PLTIMER PLTIMER - Primary Latency Timer (0x00D) on page 8-12
0x00E Byte Px_HDR HDR - Header Type Register (0x00E) on page 8-13
0x00F Byte Px_BIST BIST - Built-in Self Test Register (0x00F) on page 8-13
0x010 DWord Px_BAR0 BAR0 - Base Address Register 0 (0x010) on page 8-13
0x014 DWord Px_BAR1 BAR1 - Base Address Register 1 (0x014) on page 8-13
0x018 Byte Px_PBUSN PBUSN - Primary Bus Number Register (0x018) on page 8-13
0x019 Byte Px_SBUSN SBUSN - Secondary Bus Number Register (0x019) on page 8-13
0x01A Byte Px_SUBUSN SUBUSN - Subordinate Bus Number Register (0x01A) on page 8-14
0x01B Byte Px_SLTIMER SLTIMER - Secondary Latency Timer Register (0x01B) on page 8-14
Table 8.3 Downstream Ports 2, 4, 6 Configuration Space Registers (Part 1 of 4)
Cfg.
Offset Size
Register
Mnemonic
Register Definition
Table 8.2 Upstream Port 0 Configuration Space Registers (Part 4 of 4)