IDT Configuration Registers
PES12T3G2 User Manual
8 - 56
January 28, 2013
Notes
GPIOFUNC - General Purpose I/O Control Function (0x418)
GPIOCFG - General Purpose I/O Configuration (0x41C)
13
TEMICTL
RW
0x0
Sticky
Toggle Electromechanical Interlock Control. When this bit is
cleared, the Electromechanical Interlock (PxILOCKP) output is
pulsed for at least 100 ms and at most 150 ms when a one is writ-
ten to the EIC bit in the PCIESCTL register. When this bit is set,
writing a one to the EIC register inverts the state of the PxILOCKP
output.
15:14
RSTMODE
RW
0x0
Sticky
Reset Mode. This field controls the manner in which downstream
port reset outputs are generated.
0x0 - (pec) Power enable controlled reset output
0x1 - (pgc) Power good controlled reset output
0x2 - Reserved
0x3 - Reserved
23:16
PWR2RST
RW
0x14
Sticky
Slot Power to Reset Negation. This field contains the delay from
stable downstream port power to negation of the downstream port
reset in units of 10 mS. A value of zero corresponds to no delay.
This field may be used to meet the T
PCPERL
specification.
The default value corresponds to 200 mS.
31:24
RST2PWR
RW
0x14
Sticky
Reset Negation. This field contains the delay from negation of a
downstream port’s reset to disabling of a downstream port’s power
in units of 10 mS. A value of zero corresponds to no delay.
The default value corresponds to 200 mS.
Bit
Field
Field
Name
Type Default
Value
Description
15:0
GPIOFUNC
RW
0x0
Sticky
GPIO Function. Each bit in this field controls the corresponding
GPIO pin. When set to a one, the corresponding GPIO pin oper-
ates as the alternate function as defined in Table 4.1 of Chapter 4.
When a bit is cleared to a zero, the corresponding GPIO pin oper-
ates as a general purpose I/O pin.
31:16
Reserved
RO
0x0
Reserved field.
Bit
Field
Field
Name
Type Default
Value
Description
15:0
GPIOCFG
RW
0x0
Sticky
GPIO Configuration. Each bit in this field controls the correspond-
ing GPIO pin. When a bit is configured as a general purpose I/O
pin and the corresponding bit in this field is set, then the pin is con-
figured as a GPIO output. When a bit is configured as a general
purpose I/O pin and the corresponding bit in this field is zero, then
the pin is configured as an input. When the pin is configured as an
alternate function, the behavior of the pin is defined by the alter-
nate function.
31:16
Reserved
RO
0x0
Reserved field.
Bit
Field
Field
Name
Type Default
Value
Description
Summary of Contents for 89HPES12T3G2
Page 10: ...IDT Table of Contents PES12T3G2 User Manual iv January 28 2013 Notes...
Page 12: ...IDT List of Tables PES12T3G2 User Manual vi January 28 2013 Notes...
Page 14: ...IDT List of Figures PES12T3G2 User Manual viii January 28 2013 Notes...
Page 18: ...IDT Register List PES12T3G2 User Manual xii January 28 2013 Notes...
Page 46: ...IDT Link Operation PES12T3G2 User Manual 3 10 January 28 2013 Notes...
Page 66: ...IDT SMBus Interfaces PES12T3G2 User Manual 5 18 January 28 2013 Notes...
Page 70: ...IDT Power Management PES12T3G2 User Manual 6 4 January 28 2013 Notes...
Page 138: ...IDT Configuration Registers PES12T3G2 User Manual 8 62 January 28 2013 Notes...