IDT 89HPES12T3G2, Preliminary User'S Manual

Page: 35 / 146

IDT Clocking, Reset and Initialization
PES12T3G2 User Manual 2 - 7 January 28, 2013
Notes
When a Downstream Secondary Bus Reset occurs, the following sequence is executed.
1. If the corresponding downstream port’s link is up, TS1 ordered sets with the hot reset bit set are
transmitted
2. All TLPs received from corresponding downstream port and queued in the PES12T3G2 are
discarded.
3. Wait for software to clear the Secondary Bus Reset (SRESET) bit in the upstream port’s Bridge
Control Register (BCTL).
4. Normal downstream port operation begins.
The operation of the upstream port is unaffected by a Downstream Secondary Bus Reset.
The operation of other downstream ports is unaffected by a Downstream Secondary Bus Reset.
During a Downstream Secondary Bus Reset, Type 0 configuration read and write transactions that
target the downstream port complete normally.
During a Downstream Secondary Bus Reset, all TLPs destined to the secondary side of the downstream
port’s PCI-to-PCI bridge are treated as unsupported requests.
The operation of the slave SMBus interface is unaffected by a Downstream Secondary Bus Reset.
Downstream Port Reset Outputs
Individual downstream port reset outputs (P2RSTN and P4RSTN ) are provided as GPIO pin alternate
functions. Following a Fundamental Reset, all of the GPIO pins default to GPIO inputs. Therefore, the
downstream port resets are tri-stated. A system designer should use a pull-down on these signals if they
are used as reset outputs.
The PES12T3G2 ensures through hardware that the minimum PxRSTN assertion pulse width is no less
than 200 µ s. Downstream port reset outputs can be configured to operate in one of two modes. These
modes are power enable controlled reset output and power good controlled reset output. The downstream
port reset output mode is determined by the Reset Mode (RSTMODE) field in the Hot-Plug Configuration
Control (HPCFGCTL) register.
Power Enable Controlled Reset Output
In this mode a downstream port reset output state is controlled as a side effect of slot power being
turned on or off. The operation of this mode is illustrated in Figure 2.3. A downstream port’s slot power is
controlled by the Power Controller Control (PCC) bit in the PCI Express Slot Control (PCIESCTL) register
Figure 2.3 Power Enable Controlled Reset Output Mode Operation
While slot power is disabled, the corresponding downstream port reset output is asserted. When slot
power is enabled by writing a zero to the PCC bit, the Port x Power Enable Output (PxPEP) is asserted and
then power to the slot is enabled and the corresponding downstream port reset output is negated. The time
between the assertion of the PxPEP signal and the negation of the PxRSTN signal is controlled by the
value in the Slot Power to Reset Negation (PWR2RST) field in the HPCFGCTL register. While slot power is
enabled, the corresponding downstream port reset output is negated.
PxPEP
PxRSTN
T
PWR2RST
T
RST2PWR