IDT 89HPES12T3G2, Preliminary User'S Manual

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IDT PES12T3G2 Device Overview
PES12T3G2 User Manual 1 - 5 January 28, 2013
Notes
PE2TP[3:0]
PE2TN[3:0] O PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 2.
PE4RP[3:0]
PE4RN[3:0] I PCI Express Port 4 Serial Data Receive. Differential PCI Express receive
pairs for port 4.
PE4TP[3:0]
PE4TN[3:0] O PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 4.
PEREFCLKP[0]
PEREFCLKN[0] I PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is determined by the REFCLKM signal.
REFCLKM I PCI Express Reference Clock Mode Select. This signal selects the fre-
quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
This pin should be static and not change following the negation of
PERSTN.
Signal Type Name/Description
MSMBADDR[4:1] I Master SMBus Address. These pins determine the SMBus address of the
serial EEPROM from which configuration information is loaded.
MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize
transfers on the master SMBus.
MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the mas-
ter SMBus.
SSMBADDR[5,3:1] I Slave SMBus Address. These pins determine the SMBus address to
which the slave SMBus interface responds.
SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans-
fers on the slave SMBus.
SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave
SMBus.
Table 1.4 SMBus Interface Pins
Signal Type Name/Description
Table 1.3 PCI Express Interface Pins (Part 2 of 2)