IDT 89HPES12T3G2, Preliminary User'S Manual

Page: 142 / 146

IDT JTAG Boundary Scan
PES12T3G2 User Manual 9 - 4 January 28, 2013
Notes 
Device ID register
These registers are connected in parallel between a common serial input and a common serial data
output and are described in the following sections. For more detailed descriptions, refer to IEEE Standard
Test Access Port (IEEE Std. 1149.1).
Boundary Scan Registers
This boundary scan chain is connected between JTAG_TDI and JTAG_TDO when EXTEST or
SAMPLE/PRELOAD instructions are selected. Once EXTEST is selected and the TAP controller passes
through the UPDATE-IR state, whatever value that is currently held in the boundary scan register’s output
latches is immediately transferred to the corresponding outputs or output enables.
Therefore, the SAMPLE/PRELOAD instruction must first be used to load suitable values into the
boundary scan cells, so that inappropriate values are not driven out onto the system pins. All of the
boundary scan cells feature a negative edge latch, which guarantees that clock skew cannot cause incor-
rect data to be latched into a cell. The input cells are sample-only cells. The simplified logic configuration is
shown in Figure 9.3.
Figure 9.3 Diagram of Observe-only Input Cell
The simplified logic configuration of the output cells is shown in Figure 9.4.
Figure 9.4 Diagram of Output Cell
The output enable cells are also output cells. The simplified logic is shown in Figure 9.5.
Input
Pin
shift_dr
From previous cell
clock_dr
D Q
To next cell
To core logic
MUX
Data from Core
Data from Previous Cell
shift_dr
To Next Cell
To Output Pad
clock_dr
update_dr
MU
X
D
Q
D Q
EXTEST
MUX