IDT 89HPES12T3G2, Preliminary User'S Manual

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IDT Clocking, Reset and Initialization
PES12T3G2 User Manual 2 - 2 January 28, 2013
Notes
Reset
The PES12T3G2 defines four Conventional Reset categories: Fundamental reset, Hot Reset, Upstream
Secondary Bus Hot-Reset, and Downstream Secondary Bus Hot-Reset.
– A Fundamental Reset causes all logic in the PES12T3G2 to be returned to an initial state.
– A Hot Reset causes all logic in the PES12T3G2 to be returned to an initial state, but does not
cause the state of register fields denoted as “sticky” to be modified.
– An Upstream Secondary Bus Reset causes all devices on the virtual PCI bus to be hot reset
except the upstream port (i.e., upstream PCI to PCI bridge).
– A Downstream Secondary Bus Reset causes a hot reset to be propagated on the corresponding
external secondary bus link.
There are two sub-categories of Fundamental Reset: Cold reset and Warm reset. A Cold Reset occurs
following a device being powered on and assertion of PERSTN. A Warm Reset is a Fundamental Reset that
occurs without removal of power.
Signal
May Be
Overridden
Description
CCLKDS Y Common Clock Downstream. The assertion of this pin indicates
that all downstream ports are using the same clock source as that
provided to downstream devices.This pin is used as the initial value
of the Slot Clock Configuration bit in all of the Link Status Registers
for downstream ports. The value may be overridden by modifying
the SCLK bit in the downstream port’s PCIELSTS register.
CCLKUS Y Common Clock Upstream. The assertion of this pin indicates that
the upstream port is using the same clock source as the upstream
device. This pin is used as the initial value of the Slot Clock Configu-
ration bit in the Link Status Register for the upstream port. The value
may be overridden by modifying the SCLK bit in the downstream
port’s PCIELSTS register.
MSMBSMODE N Master SMBus Slow Mode. The assertion of this pin indicates that
the master SMBus should operate at 100 KHz instead of 400 kHz.
REFCLKM N PCI Express Reference Clock Mode Select. This signal selects
the frequency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
RSTHALT Y Reset Halt. When this signal is asserted during a PCI Express Fun-
damental Reset, the PES12T3G2 executes the reset procedure and
remains in a reset state with the Master and Slave SMBuses active.
This allows software to read and write registers internal to the device
before normal device operation begins. The device exits the reset
state when the RSTHALT bit is cleared in the SWCTL register
through the SMBus.
The value may be overridden by modifying the RSTHALT bit in the
SWCTL register.
SWMODE[2:0] N Switch Mode. These configuration pins determine the PES12T3G2
switch operating mode.
0x0 - Normal Switch Mode
0x1 - Normal Switch Mode with Serial EEPROM Initialization
0x2 through 0x7 - Reserved
Table 2.2 Boot Configuration Vector Signals