IDT 89HPES12T3G2, Preliminary User'S Manual

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IDT PES12T3G2 Device Overview
PES12T3G2 User Manual 1 - 8 January 28, 2013
Notes
JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.
JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Signal Type Name/Description
REFRES0 I/O Port 0 External Reference Resistor. Provides a reference for the Port 0
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-
tor should be connected from this pin to ground.
REFRES2 I/O Port 2 External Reference Resistor. Provides a reference for the Port 2
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-
tor should be connected from this pin to ground.
REFRES4 I/O Port 4 External Reference Resistor. Provides a reference for the Port 4
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-
tor should be connected from this pin to ground.
V
DD
CORE I Core V
DD.
Power supply for core logic.
V
DD
I/O I I/O V
DD.
LVTTL I/O buffer power supply.
V
DD
PEA I PCI Express Analog Power. Serdes analog power supply (1.0V).
V
DD
PEHA I PCI Express Analog High Power. Serdes analog power supply (2.5V).
V
DD
PETA I PCI Express Transmitter Analog Voltage. Serdes transmitter analog
power supply (1.0V).
V
SS
I Ground.
Table 1.8 Power, Ground, and SerDes Resistor Pins
Signal Type Name/Description
Table 1.7 Test Pins (Part 2 of 2)